question on i386 very early memory detection cleanup patch

["Jan Beulich" <JBeulich@novell.com>]

Is there a particular reason why this patch changes the alignment of
cpu_gdt_table to be page rather than cache line aligned? This is
particulary strange to me because the alignment is guaranteed only for
the boot processor, but not for any of the APs; for the latter ones
there isn't even a string guarantee that the table would be cache line
aligned (which it really should be); the weak guarantee only is through
an appearant assumption of GDT_ENTRIES being a sufficiently large power
of two.

Thanks, Jan