From: blaze <1466528493@qq.com>
To: kernel@esmil.dk, hal.feng@starfivetech.com
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
blaze <1466528493@qq.com>
Subject: [PATCH] clk: starfive: jh7110: Fix clk reference leak for pll0_out in jh7110_syscrg_probe()
Date: Wed, 9 Sep 2026 12:43:31 +0800 [thread overview]
Message-ID: <tencent_0D58C9974B2D7889109BACF393650FFD8706@qq.com> (raw)
In jh7110_syscrg_probe(), the handling of the three PLL clock outputs
(pll0_out, pll1_out, pll2_out) follows the same pattern: clk_get() is
called, and on success clk_put() is called before setting the pll entry
to NULL. However, the pll0_out branch is missing clk_put(), unlike
pll1_out and pll2_out which correctly call clk_put(pllclk).
Additionally, when clk_notifier_register() fails, the error path returns
without releasing the clock reference, leaking it.
Fix this by calling clk_put(pllclk) after clk_notifier_register(),
matching the pattern used for pll1_out and pll2_out. Placing clk_put()
before the error check covers both the success and error paths.
Fixes: cc46f7c9edc4 ("clk: starfive: jh7110: Add PLL clock source support")
Signed-off-by: blaze <1466528493@qq.com>
---
drivers/clk/starfive/clk-starfive-jh7110-sys.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 0000000..1111111 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -432,6 +432,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
+ clk_put(pllclk);
if (ret)
return ret;
priv->pll[0] = NULL;
--
2.43.0
next reply other threads:[~2026-09-09 4:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-09 4:43 blaze [this message]
2026-09-25 13:50 ` Brian Masney
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