* [PATCH 1/1] perf/x86/intel/uncore: Add Broadwell-DE uncore support
@ 2015-07-02 12:12 kan.liang
2015-07-10 8:20 ` Stephane Eranian
2015-08-04 9:00 ` [tip:perf/core] " tip-bot for Kan Liang
0 siblings, 2 replies; 6+ messages in thread
From: kan.liang @ 2015-07-02 12:12 UTC (permalink / raw)
To: a.p.zijlstra; +Cc: eranian, ak, linux-kernel, Kan Liang
From: Kan Liang <kan.liang@intel.com>
The uncore subsystem for Broadwell-DE is similar to Haswell-EP.
There are some differences in pci device IDs, box number and
constraints.
Please refer to the public document.
http://www.intel.com/content/www/us/en/processors/xeon/
xeon-d-1500-uncore-performance-monitoring.html
Signed-off-by: Kan Liang <kan.liang@intel.com>
---
arch/x86/kernel/cpu/perf_event_intel_uncore.c | 6 +
arch/x86/kernel/cpu/perf_event_intel_uncore.h | 2 +
.../x86/kernel/cpu/perf_event_intel_uncore_snbep.c | 164 +++++++++++++++++++++
3 files changed, 172 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 21b5e38..e255fcb 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -911,6 +911,9 @@ static int __init uncore_pci_init(void)
case 63: /* Haswell-EP */
ret = hswep_uncore_pci_init();
break;
+ case 86: /* BDX-DE */
+ ret = bdx_uncore_pci_init();
+ break;
case 42: /* Sandy Bridge */
ret = snb_uncore_pci_init();
break;
@@ -1224,6 +1227,9 @@ static int __init uncore_cpu_init(void)
case 63: /* Haswell-EP */
hswep_uncore_cpu_init();
break;
+ case 86: /* BDX-DE */
+ bdx_uncore_cpu_init();
+ break;
default:
return 0;
}
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index 0f77f0a..72c54c2 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -336,6 +336,8 @@ int ivbep_uncore_pci_init(void);
void ivbep_uncore_cpu_init(void);
int hswep_uncore_pci_init(void);
void hswep_uncore_cpu_init(void);
+int bdx_uncore_pci_init(void);
+void bdx_uncore_cpu_init(void);
/* perf_event_intel_uncore_nhmex.c */
void nhmex_uncore_cpu_init(void);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index 6d6e85d..c0f678c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -2321,3 +2321,167 @@ int hswep_uncore_pci_init(void)
return 0;
}
/* end of Haswell-EP uncore support */
+
+/* BDX-DE uncore support */
+
+static struct intel_uncore_type bdx_uncore_ubox = {
+ .name = "ubox",
+ .num_counters = 2,
+ .num_boxes = 1,
+ .perf_ctr_bits = 48,
+ .fixed_ctr_bits = 48,
+ .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
+ .event_ctl = HSWEP_U_MSR_PMON_CTL0,
+ .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
+ .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
+ .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
+ .num_shared_regs = 1,
+ .ops = &ivbep_uncore_msr_ops,
+ .format_group = &ivbep_uncore_ubox_format_group,
+};
+
+static struct event_constraint bdx_uncore_cbox_constraints[] = {
+ UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
+ UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
+ EVENT_CONSTRAINT_END
+};
+
+static struct intel_uncore_type bdx_uncore_cbox = {
+ .name = "cbox",
+ .num_counters = 4,
+ .num_boxes = 8,
+ .perf_ctr_bits = 48,
+ .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
+ .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
+ .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
+ .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
+ .msr_offset = HSWEP_CBO_MSR_OFFSET,
+ .num_shared_regs = 1,
+ .constraints = bdx_uncore_cbox_constraints,
+ .ops = &hswep_uncore_cbox_ops,
+ .format_group = &hswep_uncore_cbox_format_group,
+};
+
+static struct intel_uncore_type *bdx_msr_uncores[] = {
+ &bdx_uncore_ubox,
+ &bdx_uncore_cbox,
+ &hswep_uncore_pcu,
+ NULL,
+};
+
+void bdx_uncore_cpu_init(void)
+{
+ if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
+ bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
+ uncore_msr_uncores = bdx_msr_uncores;
+}
+
+static struct intel_uncore_type bdx_uncore_ha = {
+ .name = "ha",
+ .num_counters = 4,
+ .num_boxes = 1,
+ .perf_ctr_bits = 48,
+ SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type bdx_uncore_imc = {
+ .name = "imc",
+ .num_counters = 5,
+ .num_boxes = 2,
+ .perf_ctr_bits = 48,
+ .fixed_ctr_bits = 48,
+ .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
+ .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+ .event_descs = hswep_uncore_imc_events,
+ SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type bdx_uncore_irp = {
+ .name = "irp",
+ .num_counters = 4,
+ .num_boxes = 1,
+ .perf_ctr_bits = 48,
+ .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
+ .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
+ .ops = &hswep_uncore_irp_ops,
+ .format_group = &snbep_uncore_format_group,
+};
+
+
+static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
+ UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
+ UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
+ UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
+ UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
+ EVENT_CONSTRAINT_END
+};
+
+static struct intel_uncore_type bdx_uncore_r2pcie = {
+ .name = "r2pcie",
+ .num_counters = 4,
+ .num_boxes = 1,
+ .perf_ctr_bits = 48,
+ .constraints = bdx_uncore_r2pcie_constraints,
+ SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+enum {
+ BDX_PCI_UNCORE_HA,
+ BDX_PCI_UNCORE_IMC,
+ BDX_PCI_UNCORE_IRP,
+ BDX_PCI_UNCORE_R2PCIE,
+};
+
+static struct intel_uncore_type *bdx_pci_uncores[] = {
+ [BDX_PCI_UNCORE_HA] = &bdx_uncore_ha,
+ [BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc,
+ [BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp,
+ [BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie,
+ NULL,
+};
+
+static DEFINE_PCI_DEVICE_TABLE(bdx_uncore_pci_ids) = {
+ { /* Home Agent 0 */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
+ },
+ { /* MC0 Channel 0 */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
+ },
+ { /* MC0 Channel 1 */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
+ },
+ { /* IRP */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0),
+ },
+ { /* R2PCIe */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0),
+ },
+ { /* end: all zeroes */ }
+};
+
+static struct pci_driver bdx_uncore_pci_driver = {
+ .name = "bdx_uncore",
+ .id_table = bdx_uncore_pci_ids,
+};
+
+int bdx_uncore_pci_init(void)
+{
+ int ret = snbep_pci2phy_map_init(0x6f1e);
+
+ if (ret)
+ return ret;
+ uncore_pci_uncores = bdx_pci_uncores;
+ uncore_pci_driver = &bdx_uncore_pci_driver;
+ return 0;
+}
+
+/* end of BDX-DE uncore support */
--
1.8.3.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] perf/x86/intel/uncore: Add Broadwell-DE uncore support
2015-07-02 12:12 [PATCH 1/1] perf/x86/intel/uncore: Add Broadwell-DE uncore support kan.liang
@ 2015-07-10 8:20 ` Stephane Eranian
2015-07-13 12:51 ` Liang, Kan
2015-08-04 9:00 ` [tip:perf/core] " tip-bot for Kan Liang
1 sibling, 1 reply; 6+ messages in thread
From: Stephane Eranian @ 2015-07-10 8:20 UTC (permalink / raw)
To: Liang, Kan; +Cc: Peter Zijlstra, ak, LKML
Hi,
On Thu, Jul 2, 2015 at 5:12 AM, <kan.liang@intel.com> wrote:
>
> From: Kan Liang <kan.liang@intel.com>
>
> The uncore subsystem for Broadwell-DE is similar to Haswell-EP.
> There are some differences in pci device IDs, box number and
> constraints.
> Please refer to the public document.
> http://www.intel.com/content/www/us/en/processors/xeon/
> xeon-d-1500-uncore-performance-monitoring.html
>
> Signed-off-by: Kan Liang <kan.liang@intel.com>
> ---
> arch/x86/kernel/cpu/perf_event_intel_uncore.c | 6 +
> arch/x86/kernel/cpu/perf_event_intel_uncore.h | 2 +
> .../x86/kernel/cpu/perf_event_intel_uncore_snbep.c | 164 +++++++++++++++++++++
> 3 files changed, 172 insertions(+)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> index 21b5e38..e255fcb 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> @@ -911,6 +911,9 @@ static int __init uncore_pci_init(void)
> case 63: /* Haswell-EP */
> ret = hswep_uncore_pci_init();
> break;
> + case 86: /* BDX-DE */
> + ret = bdx_uncore_pci_init();
> + break;
> case 42: /* Sandy Bridge */
> ret = snb_uncore_pci_init();
> break;
> @@ -1224,6 +1227,9 @@ static int __init uncore_cpu_init(void)
> case 63: /* Haswell-EP */
> hswep_uncore_cpu_init();
> break;
> + case 86: /* BDX-DE */
> + bdx_uncore_cpu_init();
> + break;
> default:
> return 0;
> }
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> index 0f77f0a..72c54c2 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> @@ -336,6 +336,8 @@ int ivbep_uncore_pci_init(void);
> void ivbep_uncore_cpu_init(void);
> int hswep_uncore_pci_init(void);
> void hswep_uncore_cpu_init(void);
> +int bdx_uncore_pci_init(void);
> +void bdx_uncore_cpu_init(void);
>
> /* perf_event_intel_uncore_nhmex.c */
> void nhmex_uncore_cpu_init(void);
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
> index 6d6e85d..c0f678c 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
> @@ -2321,3 +2321,167 @@ int hswep_uncore_pci_init(void)
> return 0;
> }
> /* end of Haswell-EP uncore support */
> +
> +/* BDX-DE uncore support */
> +
> +static struct intel_uncore_type bdx_uncore_ubox = {
> + .name = "ubox",
> + .num_counters = 2,
> + .num_boxes = 1,
> + .perf_ctr_bits = 48,
> + .fixed_ctr_bits = 48,
> + .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
> + .event_ctl = HSWEP_U_MSR_PMON_CTL0,
> + .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
> + .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
> + .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
> + .num_shared_regs = 1,
> + .ops = &ivbep_uncore_msr_ops,
> + .format_group = &ivbep_uncore_ubox_format_group,
> +};
> +
> +static struct event_constraint bdx_uncore_cbox_constraints[] = {
> + UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
> + UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
> + UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
> + EVENT_CONSTRAINT_END
> +};
> +
> +static struct intel_uncore_type bdx_uncore_cbox = {
> + .name = "cbox",
> + .num_counters = 4,
> + .num_boxes = 8,
> + .perf_ctr_bits = 48,
> + .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
> + .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
> + .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
> + .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
> + .msr_offset = HSWEP_CBO_MSR_OFFSET,
> + .num_shared_regs = 1,
> + .constraints = bdx_uncore_cbox_constraints,
> + .ops = &hswep_uncore_cbox_ops,
> + .format_group = &hswep_uncore_cbox_format_group,
> +};
> +
> +static struct intel_uncore_type *bdx_msr_uncores[] = {
> + &bdx_uncore_ubox,
> + &bdx_uncore_cbox,
> + &hswep_uncore_pcu,
> + NULL,
> +};
> +
> +void bdx_uncore_cpu_init(void)
> +{
> + if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
> + bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
> + uncore_msr_uncores = bdx_msr_uncores;
> +}
> +
> +static struct intel_uncore_type bdx_uncore_ha = {
> + .name = "ha",
> + .num_counters = 4,
> + .num_boxes = 1,
> + .perf_ctr_bits = 48,
> + SNBEP_UNCORE_PCI_COMMON_INIT(),
> +};
> +
> +static struct intel_uncore_type bdx_uncore_imc = {
> + .name = "imc",
> + .num_counters = 5,
> + .num_boxes = 2,
> + .perf_ctr_bits = 48,
> + .fixed_ctr_bits = 48,
> + .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
> + .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
> + .event_descs = hswep_uncore_imc_events,
> + SNBEP_UNCORE_PCI_COMMON_INIT(),
> +};
> +
> +static struct intel_uncore_type bdx_uncore_irp = {
> + .name = "irp",
> + .num_counters = 4,
> + .num_boxes = 1,
> + .perf_ctr_bits = 48,
> + .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
> + .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
> + .ops = &hswep_uncore_irp_ops,
> + .format_group = &snbep_uncore_format_group,
> +};
> +
> +
> +static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
> + UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
> + UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
> + UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
> + UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
> + UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
> + UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
> + UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
> + EVENT_CONSTRAINT_END
> +};
> +
> +static struct intel_uncore_type bdx_uncore_r2pcie = {
> + .name = "r2pcie",
> + .num_counters = 4,
> + .num_boxes = 1,
> + .perf_ctr_bits = 48,
> + .constraints = bdx_uncore_r2pcie_constraints,
> + SNBEP_UNCORE_PCI_COMMON_INIT(),
> +};
> +
> +enum {
> + BDX_PCI_UNCORE_HA,
> + BDX_PCI_UNCORE_IMC,
> + BDX_PCI_UNCORE_IRP,
> + BDX_PCI_UNCORE_R2PCIE,
> +};
> +
> +static struct intel_uncore_type *bdx_pci_uncores[] = {
> + [BDX_PCI_UNCORE_HA] = &bdx_uncore_ha,
> + [BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc,
> + [BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp,
> + [BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie,
> + NULL,
> +};
> +
> +static DEFINE_PCI_DEVICE_TABLE(bdx_uncore_pci_ids) = {
> + { /* Home Agent 0 */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
> + .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
> + },
> + { /* MC0 Channel 0 */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
> + .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
> + },
> + { /* MC0 Channel 1 */
> + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
> + .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
> + },
Are you sure about the two PCI id for the IMCs (0x6fb0, 0x6fb1) ?
I do not see them on my system?
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/1] perf/x86/intel/uncore: Add Broadwell-DE uncore support
2015-07-10 8:20 ` Stephane Eranian
@ 2015-07-13 12:51 ` Liang, Kan
2015-08-26 15:12 ` Liang, Kan
0 siblings, 1 reply; 6+ messages in thread
From: Liang, Kan @ 2015-07-13 12:51 UTC (permalink / raw)
To: Stephane Eranian; +Cc: Peter Zijlstra, ak, LKML
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1024 bytes --]
> > + },
> > + { /* MC0 Channel 0 */
> > + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
> > + .driver_data =
> UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
> > + },
> > + { /* MC0 Channel 1 */
> > + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
> > + .driver_data =
> UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
> > + },
>
> Are you sure about the two PCI id for the IMCs (0x6fb0, 0x6fb1) ?
> I do not see them on my system?
Yes, the PCI id is correct. You cannot see them is because they
are hide by BIOS. I've already sent a request to BIOS team to
unhide them. I will let you know the updated BIOS version,
once I get feedback from them.
BTW, I've verified the PCI id in BDX-EP with corrected BIOS. IMCs
counter works well. EP and DE are same for iMC0CH0 and iMC0CH1.
Thanks,
Kan
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [tip:perf/core] perf/x86/intel/uncore: Add Broadwell-DE uncore support
2015-07-02 12:12 [PATCH 1/1] perf/x86/intel/uncore: Add Broadwell-DE uncore support kan.liang
2015-07-10 8:20 ` Stephane Eranian
@ 2015-08-04 9:00 ` tip-bot for Kan Liang
1 sibling, 0 replies; 6+ messages in thread
From: tip-bot for Kan Liang @ 2015-08-04 9:00 UTC (permalink / raw)
To: linux-tip-commits
Cc: mingo, hpa, linux-kernel, peterz, torvalds, kan.liang, tglx
Commit-ID: 070e98873cf7196cad58f8b6e5278dd5533c81f0
Gitweb: http://git.kernel.org/tip/070e98873cf7196cad58f8b6e5278dd5533c81f0
Author: Kan Liang <kan.liang@intel.com>
AuthorDate: Thu, 2 Jul 2015 08:12:52 -0400
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 4 Aug 2015 10:17:00 +0200
perf/x86/intel/uncore: Add Broadwell-DE uncore support
The uncore subsystem for Broadwell-DE is similar to Haswell-EP. There
are some differences in pci device IDs, box number and constraints.
Please refer to the public document:
http://www.intel.com/content/www/us/en/processors/xeon/xeon-d-1500-uncore-performance-monitoring.html
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1435839172-15114-1-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/perf_event_intel_uncore.c | 6 +
arch/x86/kernel/cpu/perf_event_intel_uncore.h | 2 +
.../x86/kernel/cpu/perf_event_intel_uncore_snbep.c | 164 +++++++++++++++++++++
3 files changed, 172 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index c2af967..560e525 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -911,6 +911,9 @@ static int __init uncore_pci_init(void)
case 63: /* Haswell-EP */
ret = hswep_uncore_pci_init();
break;
+ case 86: /* BDX-DE */
+ ret = bdx_uncore_pci_init();
+ break;
case 42: /* Sandy Bridge */
ret = snb_uncore_pci_init();
break;
@@ -1229,6 +1232,9 @@ static int __init uncore_cpu_init(void)
case 63: /* Haswell-EP */
hswep_uncore_cpu_init();
break;
+ case 86: /* BDX-DE */
+ bdx_uncore_cpu_init();
+ break;
default:
return 0;
}
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index 0f77f0a..72c54c2 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -336,6 +336,8 @@ int ivbep_uncore_pci_init(void);
void ivbep_uncore_cpu_init(void);
int hswep_uncore_pci_init(void);
void hswep_uncore_cpu_init(void);
+int bdx_uncore_pci_init(void);
+void bdx_uncore_cpu_init(void);
/* perf_event_intel_uncore_nhmex.c */
void nhmex_uncore_cpu_init(void);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index 76a3feb..694510a8 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -2321,3 +2321,167 @@ int hswep_uncore_pci_init(void)
return 0;
}
/* end of Haswell-EP uncore support */
+
+/* BDX-DE uncore support */
+
+static struct intel_uncore_type bdx_uncore_ubox = {
+ .name = "ubox",
+ .num_counters = 2,
+ .num_boxes = 1,
+ .perf_ctr_bits = 48,
+ .fixed_ctr_bits = 48,
+ .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
+ .event_ctl = HSWEP_U_MSR_PMON_CTL0,
+ .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
+ .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
+ .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
+ .num_shared_regs = 1,
+ .ops = &ivbep_uncore_msr_ops,
+ .format_group = &ivbep_uncore_ubox_format_group,
+};
+
+static struct event_constraint bdx_uncore_cbox_constraints[] = {
+ UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
+ UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
+ EVENT_CONSTRAINT_END
+};
+
+static struct intel_uncore_type bdx_uncore_cbox = {
+ .name = "cbox",
+ .num_counters = 4,
+ .num_boxes = 8,
+ .perf_ctr_bits = 48,
+ .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
+ .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
+ .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
+ .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
+ .msr_offset = HSWEP_CBO_MSR_OFFSET,
+ .num_shared_regs = 1,
+ .constraints = bdx_uncore_cbox_constraints,
+ .ops = &hswep_uncore_cbox_ops,
+ .format_group = &hswep_uncore_cbox_format_group,
+};
+
+static struct intel_uncore_type *bdx_msr_uncores[] = {
+ &bdx_uncore_ubox,
+ &bdx_uncore_cbox,
+ &hswep_uncore_pcu,
+ NULL,
+};
+
+void bdx_uncore_cpu_init(void)
+{
+ if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
+ bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
+ uncore_msr_uncores = bdx_msr_uncores;
+}
+
+static struct intel_uncore_type bdx_uncore_ha = {
+ .name = "ha",
+ .num_counters = 4,
+ .num_boxes = 1,
+ .perf_ctr_bits = 48,
+ SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type bdx_uncore_imc = {
+ .name = "imc",
+ .num_counters = 5,
+ .num_boxes = 2,
+ .perf_ctr_bits = 48,
+ .fixed_ctr_bits = 48,
+ .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
+ .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+ .event_descs = hswep_uncore_imc_events,
+ SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type bdx_uncore_irp = {
+ .name = "irp",
+ .num_counters = 4,
+ .num_boxes = 1,
+ .perf_ctr_bits = 48,
+ .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
+ .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
+ .ops = &hswep_uncore_irp_ops,
+ .format_group = &snbep_uncore_format_group,
+};
+
+
+static struct event_constraint bdx_uncore_r2pcie_constraints[] = {
+ UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
+ UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
+ UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
+ UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
+ EVENT_CONSTRAINT_END
+};
+
+static struct intel_uncore_type bdx_uncore_r2pcie = {
+ .name = "r2pcie",
+ .num_counters = 4,
+ .num_boxes = 1,
+ .perf_ctr_bits = 48,
+ .constraints = bdx_uncore_r2pcie_constraints,
+ SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+enum {
+ BDX_PCI_UNCORE_HA,
+ BDX_PCI_UNCORE_IMC,
+ BDX_PCI_UNCORE_IRP,
+ BDX_PCI_UNCORE_R2PCIE,
+};
+
+static struct intel_uncore_type *bdx_pci_uncores[] = {
+ [BDX_PCI_UNCORE_HA] = &bdx_uncore_ha,
+ [BDX_PCI_UNCORE_IMC] = &bdx_uncore_imc,
+ [BDX_PCI_UNCORE_IRP] = &bdx_uncore_irp,
+ [BDX_PCI_UNCORE_R2PCIE] = &bdx_uncore_r2pcie,
+ NULL,
+};
+
+static DEFINE_PCI_DEVICE_TABLE(bdx_uncore_pci_ids) = {
+ { /* Home Agent 0 */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
+ },
+ { /* MC0 Channel 0 */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
+ },
+ { /* MC0 Channel 1 */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
+ },
+ { /* IRP */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0),
+ },
+ { /* R2PCIe */
+ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34),
+ .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0),
+ },
+ { /* end: all zeroes */ }
+};
+
+static struct pci_driver bdx_uncore_pci_driver = {
+ .name = "bdx_uncore",
+ .id_table = bdx_uncore_pci_ids,
+};
+
+int bdx_uncore_pci_init(void)
+{
+ int ret = snbep_pci2phy_map_init(0x6f1e);
+
+ if (ret)
+ return ret;
+ uncore_pci_uncores = bdx_pci_uncores;
+ uncore_pci_driver = &bdx_uncore_pci_driver;
+ return 0;
+}
+
+/* end of BDX-DE uncore support */
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/1] perf/x86/intel/uncore: Add Broadwell-DE uncore support
2015-07-13 12:51 ` Liang, Kan
@ 2015-08-26 15:12 ` Liang, Kan
2015-08-26 15:13 ` Stephane Eranian
0 siblings, 1 reply; 6+ messages in thread
From: Liang, Kan @ 2015-08-26 15:12 UTC (permalink / raw)
To: 'Stephane Eranian'
Cc: 'Peter Zijlstra', 'ak@linux.intel.com', 'LKML'
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1183 bytes --]
>
> > > + },
> > > + { /* MC0 Channel 0 */
> > > + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
> > > + .driver_data =
> > UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
> > > + },
> > > + { /* MC0 Channel 1 */
> > > + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
> > > + .driver_data =
> > UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
> > > + },
> >
> > Are you sure about the two PCI id for the IMCs (0x6fb0, 0x6fb1) ?
> > I do not see them on my system?
>
> Yes, the PCI id is correct. You cannot see them is because they are hide by
> BIOS. I've already sent a request to BIOS team to unhide them. I will let you
> know the updated BIOS version, once I get feedback from them.
> BTW, I've verified the PCI id in BDX-EP with corrected BIOS. IMCs counter
> works well. EP and DE are same for iMC0CH0 and iMC0CH1.
>
Hi Stephane,
The issue has been fixed since BIOS 76V12 for BDX-DE.
You may update the BIOS to unhide IMC counter.
Thanks,
Kan
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] perf/x86/intel/uncore: Add Broadwell-DE uncore support
2015-08-26 15:12 ` Liang, Kan
@ 2015-08-26 15:13 ` Stephane Eranian
0 siblings, 0 replies; 6+ messages in thread
From: Stephane Eranian @ 2015-08-26 15:13 UTC (permalink / raw)
To: Liang, Kan; +Cc: Peter Zijlstra, ak, LKML
On Wed, Aug 26, 2015 at 8:12 AM, Liang, Kan <kan.liang@intel.com> wrote:
>>
>> > > + },
>> > > + { /* MC0 Channel 0 */
>> > > + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
>> > > + .driver_data =
>> > UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
>> > > + },
>> > > + { /* MC0 Channel 1 */
>> > > + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
>> > > + .driver_data =
>> > UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 1),
>> > > + },
>> >
>> > Are you sure about the two PCI id for the IMCs (0x6fb0, 0x6fb1) ?
>> > I do not see them on my system?
>>
>> Yes, the PCI id is correct. You cannot see them is because they are hide by
>> BIOS. I've already sent a request to BIOS team to unhide them. I will let you
>> know the updated BIOS version, once I get feedback from them.
>> BTW, I've verified the PCI id in BDX-EP with corrected BIOS. IMCs counter
>> works well. EP and DE are same for iMC0CH0 and iMC0CH1.
>>
>
> Hi Stephane,
>
> The issue has been fixed since BIOS 76V12 for BDX-DE.
> You may update the BIOS to unhide IMC counter.
>
Thanks for following up. The problem has been fixed now.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-08-26 15:13 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-07-02 12:12 [PATCH 1/1] perf/x86/intel/uncore: Add Broadwell-DE uncore support kan.liang
2015-07-10 8:20 ` Stephane Eranian
2015-07-13 12:51 ` Liang, Kan
2015-08-26 15:12 ` Liang, Kan
2015-08-26 15:13 ` Stephane Eranian
2015-08-04 9:00 ` [tip:perf/core] " tip-bot for Kan Liang
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