* [PATCH] perf, x86: Fix key index in Pentium-4 PMU
@ 2010-03-19 7:28 Lin Ming
2010-03-19 8:25 ` [tip:perf/core] perf, x86: Fix key indexing " tip-bot for Lin Ming
0 siblings, 1 reply; 2+ messages in thread
From: Lin Ming @ 2010-03-19 7:28 UTC (permalink / raw)
To: Cyrill Gorcunov, Ingo Molnar, Peter Zijlstra; +Cc: lkml
Index 0-6 in p4_templates are reserved for common hardware events.
So p4_templates is arranged as below,
0 - 6: common hardware events
7 - N: cache events
N+1 - ...: other raw events
Reported-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
---
arch/x86/include/asm/perf_event_p4.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 2a1a57f..facf961 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -709,7 +709,7 @@ enum P4_EVENTS_ATTR {
};
enum {
- KEY_P4_L1D_OP_READ_RESULT_MISS,
+ KEY_P4_L1D_OP_READ_RESULT_MISS = PERF_COUNT_HW_MAX,
KEY_P4_LL_OP_READ_RESULT_MISS,
KEY_P4_DTLB_OP_READ_RESULT_MISS,
KEY_P4_DTLB_OP_WRITE_RESULT_MISS,
^ permalink raw reply [flat|nested] 2+ messages in thread* [tip:perf/core] perf, x86: Fix key indexing in Pentium-4 PMU
2010-03-19 7:28 [PATCH] perf, x86: Fix key index in Pentium-4 PMU Lin Ming
@ 2010-03-19 8:25 ` tip-bot for Lin Ming
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot for Lin Ming @ 2010-03-19 8:25 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, hpa, mingo, gorcunov, peterz, ming.m.lin, tglx, mingo
Commit-ID: 40b7e05e17eef31ff30fe08dfc2424ef653a792c
Gitweb: http://git.kernel.org/tip/40b7e05e17eef31ff30fe08dfc2424ef653a792c
Author: Lin Ming <ming.m.lin@intel.com>
AuthorDate: Fri, 19 Mar 2010 15:28:58 +0800
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Fri, 19 Mar 2010 09:23:17 +0100
perf, x86: Fix key indexing in Pentium-4 PMU
Index 0-6 in p4_templates are reserved for common hardware
events. So p4_templates is arranged as below:
0 - 6: common hardware events
7 - N: cache events
N+1 - ...: other raw events
Reported-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Acked-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Peter Zijlstra <peterz@infradead.org>
LKML-Reference: <1268983738.13901.142.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/include/asm/perf_event_p4.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 2a1a57f..facf961 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -709,7 +709,7 @@ enum P4_EVENTS_ATTR {
};
enum {
- KEY_P4_L1D_OP_READ_RESULT_MISS,
+ KEY_P4_L1D_OP_READ_RESULT_MISS = PERF_COUNT_HW_MAX,
KEY_P4_LL_OP_READ_RESULT_MISS,
KEY_P4_DTLB_OP_READ_RESULT_MISS,
KEY_P4_DTLB_OP_WRITE_RESULT_MISS,
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2010-03-19 8:25 UTC | newest]
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