* [tip:x86/cpu] x86, cpu: Clean up AMD erratum 400 workaround [not found] <1276681733-10872-2-git-send-email-hans.rosenfeld@amd.com> @ 2010-06-17 17:07 ` tip-bot for Hans Rosenfeld 0 siblings, 0 replies; 2+ messages in thread From: tip-bot for Hans Rosenfeld @ 2010-06-17 17:07 UTC (permalink / raw) To: linux-tip-commits; +Cc: linux-kernel, hans.rosenfeld, hpa, mingo, tglx Commit-ID: 63946e5f5436b1f30f9680ea877c6fdff0e2e177 Gitweb: http://git.kernel.org/tip/63946e5f5436b1f30f9680ea877c6fdff0e2e177 Author: Hans Rosenfeld <hans.rosenfeld@amd.com> AuthorDate: Wed, 16 Jun 2010 11:48:53 +0200 Committer: H. Peter Anvin <hpa@zytor.com> CommitDate: Wed, 16 Jun 2010 17:28:15 -0700 x86, cpu: Clean up AMD erratum 400 workaround Remove check_c1e_idle() and use the new AMD errata checking framework instead. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> LKML-Reference: <1276681733-10872-2-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> --- arch/x86/include/asm/processor.h | 4 +++ arch/x86/kernel/process.c | 39 +------------------------------------ 2 files changed, 6 insertions(+), 37 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 09fb3a1..dd89042 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -1053,6 +1053,10 @@ extern bool cpu_has_amd_erratum(const struct cpuinfo_x86 *, bool, ...); #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) +#define AMD_ERRATUM_400 \ + AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), \ + AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)) + #endif /* CONFIG_CPU_SUP_AMD */ #endif /* _ASM_X86_PROCESSOR_H */ diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index e7e3521..c288239 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -525,42 +525,6 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) return (edx & MWAIT_EDX_C1); } -/* - * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e. - * For more information see - * - Erratum #400 for NPT family 0xf and family 0x10 CPUs - * - Erratum #365 for family 0x11 (not affected because C1e not in use) - */ -static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) -{ - u64 val; - if (c->x86_vendor != X86_VENDOR_AMD) - goto no_c1e_idle; - - /* Family 0x0f models < rev F do not have C1E */ - if (c->x86 == 0x0F && c->x86_model >= 0x40) - return 1; - - if (c->x86 == 0x10) { - /* - * check OSVW bit for CPUs that are not affected - * by erratum #400 - */ - if (cpu_has(c, X86_FEATURE_OSVW)) { - rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val); - if (val >= 2) { - rdmsrl(MSR_AMD64_OSVW_STATUS, val); - if (!(val & BIT(1))) - goto no_c1e_idle; - } - } - return 1; - } - -no_c1e_idle: - return 0; -} - static cpumask_var_t c1e_mask; static int c1e_detected; @@ -638,7 +602,8 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) */ printk(KERN_INFO "using mwait in idle threads.\n"); pm_idle = mwait_idle; - } else if (check_c1e_idle(c)) { + } else if (cpu_has_amd_erratum(c, AMD_ERRATUM_400)) { + /* E400: APIC timer interrupt does not wake up CPU from C1e */ printk(KERN_INFO "using C1E aware idle routine\n"); pm_idle = c1e_idle; } else ^ permalink raw reply [flat|nested] 2+ messages in thread
[parent not found: <1280336972-865982-2-git-send-email-hans.rosenfeld@amd.com>]
* [tip:x86/cpu] x86, cpu: Clean up AMD erratum 400 workaround [not found] <1280336972-865982-2-git-send-email-hans.rosenfeld@amd.com> @ 2010-07-28 23:28 ` tip-bot for Hans Rosenfeld 0 siblings, 0 replies; 2+ messages in thread From: tip-bot for Hans Rosenfeld @ 2010-07-28 23:28 UTC (permalink / raw) To: linux-tip-commits; +Cc: linux-kernel, hans.rosenfeld, hpa, mingo, tglx, hpa Commit-ID: 9d8888c2a214aece2494a49e699a097c2ba9498b Gitweb: http://git.kernel.org/tip/9d8888c2a214aece2494a49e699a097c2ba9498b Author: Hans Rosenfeld <hans.rosenfeld@amd.com> AuthorDate: Wed, 28 Jul 2010 19:09:31 +0200 Committer: H. Peter Anvin <hpa@linux.intel.com> CommitDate: Wed, 28 Jul 2010 13:12:11 -0700 x86, cpu: Clean up AMD erratum 400 workaround Remove check_c1e_idle() and use the new AMD errata checking framework instead. Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com> LKML-Reference: <1280336972-865982-2-git-send-email-hans.rosenfeld@amd.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/amd.c | 5 ++++ arch/x86/kernel/process.c | 39 +------------------------------------ 3 files changed, 8 insertions(+), 37 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 5084c2f..eebdc1f 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -1029,6 +1029,7 @@ unsigned long calc_aperfmperf_ratio(struct aperfmperf *old, * AMD errata checking */ #ifdef CONFIG_CPU_SUP_AMD +extern const int amd_erratum_400[]; extern bool cpu_has_amd_erratum(const int *); #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 8066541..a62a4ae 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -628,6 +628,11 @@ cpu_dev_register(amd_cpu_dev); * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); */ +const int amd_erratum_400[] = + AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), + AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); + + bool cpu_has_amd_erratum(const int *erratum) { struct cpuinfo_x86 *cpu = ¤t_cpu_data; diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index e7e3521..553b02f 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -525,42 +525,6 @@ static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) return (edx & MWAIT_EDX_C1); } -/* - * Check for AMD CPUs, where APIC timer interrupt does not wake up CPU from C1e. - * For more information see - * - Erratum #400 for NPT family 0xf and family 0x10 CPUs - * - Erratum #365 for family 0x11 (not affected because C1e not in use) - */ -static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c) -{ - u64 val; - if (c->x86_vendor != X86_VENDOR_AMD) - goto no_c1e_idle; - - /* Family 0x0f models < rev F do not have C1E */ - if (c->x86 == 0x0F && c->x86_model >= 0x40) - return 1; - - if (c->x86 == 0x10) { - /* - * check OSVW bit for CPUs that are not affected - * by erratum #400 - */ - if (cpu_has(c, X86_FEATURE_OSVW)) { - rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, val); - if (val >= 2) { - rdmsrl(MSR_AMD64_OSVW_STATUS, val); - if (!(val & BIT(1))) - goto no_c1e_idle; - } - } - return 1; - } - -no_c1e_idle: - return 0; -} - static cpumask_var_t c1e_mask; static int c1e_detected; @@ -638,7 +602,8 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) */ printk(KERN_INFO "using mwait in idle threads.\n"); pm_idle = mwait_idle; - } else if (check_c1e_idle(c)) { + } else if (cpu_has_amd_erratum(amd_erratum_400)) { + /* E400: APIC timer interrupt does not wake up CPU from C1e */ printk(KERN_INFO "using C1E aware idle routine\n"); pm_idle = c1e_idle; } else ^ permalink raw reply [flat|nested] 2+ messages in thread
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2010-06-17 17:07 ` [tip:x86/cpu] x86, cpu: Clean up AMD erratum 400 workaround tip-bot for Hans Rosenfeld
[not found] <1280336972-865982-2-git-send-email-hans.rosenfeld@amd.com>
2010-07-28 23:28 ` tip-bot for Hans Rosenfeld
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