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From: tip-bot for Andre Przywara <andre.przywara@amd.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@redhat.com,
	andre.przywara@amd.com, tglx@linutronix.de, hpa@linux.intel.com
Subject: [tip:x86/cpu] x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit
Date: Wed, 8 Sep 2010 21:27:47 GMT	[thread overview]
Message-ID: <tip-7ef8aa72ab176e0288f363d1247079732c5d5792@git.kernel.org> (raw)
In-Reply-To: <1283778860-26843-2-git-send-email-andre.przywara@amd.com>

Commit-ID:  7ef8aa72ab176e0288f363d1247079732c5d5792
Gitweb:     http://git.kernel.org/tip/7ef8aa72ab176e0288f363d1247079732c5d5792
Author:     Andre Przywara <andre.przywara@amd.com>
AuthorDate: Mon, 6 Sep 2010 15:14:17 +0200
Committer:  H. Peter Anvin <hpa@linux.intel.com>
CommitDate: Wed, 8 Sep 2010 13:32:55 -0700

x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit

The AMD SSE5 feature set as-it has been replaced by some extensions
to the AVX instruction set. Thus the bit formerly advertised as SSE5
is re-used for one of these extensions (XOP).
Although this changes the /proc/cpuinfo output, it is not user visible, as
there are no CPUs (yet) having this feature.
To avoid confusion this should be added to the stable series, too.

Cc: stable@kernel.org [.32.x .34.x, .35.x]
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
LKML-Reference: <1283778860-26843-2-git-send-email-andre.przywara@amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
---
 arch/x86/include/asm/cpufeature.h |    2 +-
 arch/x86/kvm/x86.c                |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 781a50b..c9c73d8 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -152,7 +152,7 @@
 #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
 #define X86_FEATURE_OSVW	(6*32+ 9) /* OS Visible Workaround */
 #define X86_FEATURE_IBS		(6*32+10) /* Instruction Based Sampling */
-#define X86_FEATURE_SSE5	(6*32+11) /* SSE-5 */
+#define X86_FEATURE_XOP		(6*32+11) /* extended AVX instructions */
 #define X86_FEATURE_SKINIT	(6*32+12) /* SKINIT/STGI instructions */
 #define X86_FEATURE_WDT		(6*32+13) /* Watchdog timer */
 #define X86_FEATURE_NODEID_MSR	(6*32+19) /* NodeId MSR */
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 3a09c62..dd54779 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1996,7 +1996,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
 	const u32 kvm_supported_word6_x86_features =
 		F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
 		F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
-		F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
+		F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
 		0 /* SKINIT */ | 0 /* WDT */;
 
 	/* all calls to cpuid_count() should be made on the same cpu */

  reply	other threads:[~2010-09-08 21:28 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-09-06 13:14 [PATCH 0/4 -v2] x86: update AMD CPUID bits Andre Przywara
2010-09-06 13:14 ` [PATCH 1/4] x86: Fix misnamed AMD CPUID feature bit Andre Przywara
2010-09-08 21:27   ` tip-bot for Andre Przywara [this message]
2010-09-06 13:14 ` [PATCH 2/4] x86: Update AMD CPUID feature bits Andre Przywara
2010-09-08 21:28   ` [tip:x86/cpu] x86, cpu: " tip-bot for Andre Przywara
2010-09-06 13:14 ` [PATCH 3/4] x86: Fix allowed CPUID bits for KVM guests Andre Przywara
2010-09-06 18:47   ` Avi Kivity
2010-09-08 21:28   ` [tip:x86/cpu] x86, cpu: " tip-bot for Andre Przywara
2010-09-06 13:14 ` [PATCH 4/4] x86, kvm: add new AMD SVM feature bits Andre Przywara
2010-09-08 21:28   ` [tip:x86/cpu] " tip-bot for Andre Przywara

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