* [PATCH] i386: do a global tlb flush in S4 resume @ 2010-03-04 1:23 Shaohua Li 2010-03-04 2:30 ` H. Peter Anvin 0 siblings, 1 reply; 11+ messages in thread From: Shaohua Li @ 2010-03-04 1:23 UTC (permalink / raw) To: linux-kernel; +Cc: rjw, mingo, hpa, colin.king, Shaohua Li Colin reported a strange oops in S4 resume code path (see below). The test system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. The oops always happen a virtual address 0xc03ff000, which is mapped to the last 4k of first 4M memory. Doing a global tlb flush fixes the issue. EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 EIP is at copy_loop+0xe/0x15 EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 ... ... CR2: 00000000c03ff000 Tested-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Shaohua Li <shaohua.li@intel.com> --- arch/x86/power/hibernate_asm_32.S | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S index b641388..9e4ef64 100644 --- a/arch/x86/power/hibernate_asm_32.S +++ b/arch/x86/power/hibernate_asm_32.S @@ -27,10 +27,21 @@ ENTRY(swsusp_arch_suspend) ret ENTRY(restore_image) + movl mmu_cr4_features, %ecx movl resume_pg_dir, %eax subl $__PAGE_OFFSET, %eax movl %eax, %cr3 + jecxz 1f # cr4 Pentium and higher, skip if zero + movl %ecx, %edx + andl $~(X86_CR4_PGE), %edx + movl %edx, %cr4; # turn off PGE +1: + movl %cr3, %eax; # flush TLB + movl %eax, %cr3 + jecxz 1f # cr4 Pentium and higher, skip if zero + movl %ecx, %cr4; # turn PGE back on +1: movl restore_pblist, %edx .p2align 4,,7 -- 1.6.3.3 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] i386: do a global tlb flush in S4 resume 2010-03-04 1:23 [PATCH] i386: do a global tlb flush in S4 resume Shaohua Li @ 2010-03-04 2:30 ` H. Peter Anvin 2010-03-04 2:41 ` Shaohua Li 0 siblings, 1 reply; 11+ messages in thread From: H. Peter Anvin @ 2010-03-04 2:30 UTC (permalink / raw) To: Shaohua Li; +Cc: linux-kernel, rjw, mingo, colin.king On 03/03/2010 05:23 PM, Shaohua Li wrote: > Colin reported a strange oops in S4 resume code path (see below). The test > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > The oops always happen a virtual address 0xc03ff000, which is mapped to the > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > EIP is at copy_loop+0xe/0x15 > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > ... > ... > CR2: 00000000c03ff000 > > Tested-by: Colin Ian King <colin.king@canonical.com> > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > --- > arch/x86/power/hibernate_asm_32.S | 11 +++++++++++ > 1 files changed, 11 insertions(+), 0 deletions(-) > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > index b641388..9e4ef64 100644 > --- a/arch/x86/power/hibernate_asm_32.S > +++ b/arch/x86/power/hibernate_asm_32.S > @@ -27,10 +27,21 @@ ENTRY(swsusp_arch_suspend) > ret > > ENTRY(restore_image) > + movl mmu_cr4_features, %ecx > movl resume_pg_dir, %eax > subl $__PAGE_OFFSET, %eax > movl %eax, %cr3 > > + jecxz 1f # cr4 Pentium and higher, skip if zero > + movl %ecx, %edx > + andl $~(X86_CR4_PGE), %edx > + movl %edx, %cr4; # turn off PGE > +1: > + movl %cr3, %eax; # flush TLB > + movl %eax, %cr3 > + jecxz 1f # cr4 Pentium and higher, skip if zero > + movl %ecx, %cr4; # turn PGE back on > +1: > movl restore_pblist, %edx > .p2align 4,,7 > Since we're about to do another global page flush a bit further down in the same code, why not just leave PGE off until then? -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] i386: do a global tlb flush in S4 resume 2010-03-04 2:30 ` H. Peter Anvin @ 2010-03-04 2:41 ` Shaohua Li 2010-03-04 19:49 ` Rafael J. Wysocki 0 siblings, 1 reply; 11+ messages in thread From: Shaohua Li @ 2010-03-04 2:41 UTC (permalink / raw) To: H. Peter Anvin; +Cc: linux-kernel, rjw, mingo, colin.king On Thu, Mar 04, 2010 at 10:30:02AM +0800, H. Peter Anvin wrote: > On 03/03/2010 05:23 PM, Shaohua Li wrote: > > Colin reported a strange oops in S4 resume code path (see below). The test > > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > > The oops always happen a virtual address 0xc03ff000, which is mapped to the > > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > > EIP is at copy_loop+0xe/0x15 > > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > > ... > > ... > > CR2: 00000000c03ff000 > > > > Tested-by: Colin Ian King <colin.king@canonical.com> > > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > --- > > arch/x86/power/hibernate_asm_32.S | 11 +++++++++++ > > 1 files changed, 11 insertions(+), 0 deletions(-) > > > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > > index b641388..9e4ef64 100644 > > --- a/arch/x86/power/hibernate_asm_32.S > > +++ b/arch/x86/power/hibernate_asm_32.S > > @@ -27,10 +27,21 @@ ENTRY(swsusp_arch_suspend) > > ret > > > > ENTRY(restore_image) > > + movl mmu_cr4_features, %ecx > > movl resume_pg_dir, %eax > > subl $__PAGE_OFFSET, %eax > > movl %eax, %cr3 > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > + movl %ecx, %edx > > + andl $~(X86_CR4_PGE), %edx > > + movl %edx, %cr4; # turn off PGE > > +1: > > + movl %cr3, %eax; # flush TLB > > + movl %eax, %cr3 > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > + movl %ecx, %cr4; # turn PGE back on > > +1: > > movl restore_pblist, %edx > > .p2align 4,,7 > > > > Since we're about to do another global page flush a bit further down in > the same code, why not just leave PGE off until then? sure, updated patch. i386: do a global tlb flush in S4 resume Colin reported a strange oops in S4 resume code path (see below). The test system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. The oops always happen a virtual address 0xc03ff000, which is mapped to the last 4k of first 4M memory. Doing a global tlb flush fixes the issue. EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 EIP is at copy_loop+0xe/0x15 EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 ... ... CR2: 00000000c03ff000 Tested-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Shaohua Li <shaohua.li@intel.com> diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S index b641388..cd5e878 100644 --- a/arch/x86/power/hibernate_asm_32.S +++ b/arch/x86/power/hibernate_asm_32.S @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) ret ENTRY(restore_image) + movl mmu_cr4_features, %ecx movl resume_pg_dir, %eax subl $__PAGE_OFFSET, %eax movl %eax, %cr3 + jecxz 1f # cr4 Pentium and higher, skip if zero + andl $~(X86_CR4_PGE), %ecx + movl %ecx, %cr4; # turn off PGE + movl %cr3, %eax; # flush TLB + movl %eax, %cr3 +1: movl restore_pblist, %edx .p2align 4,,7 ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] i386: do a global tlb flush in S4 resume 2010-03-04 2:41 ` Shaohua Li @ 2010-03-04 19:49 ` Rafael J. Wysocki 2010-03-04 20:11 ` Rafael J. Wysocki 2010-03-05 0:59 ` Shaohua Li 0 siblings, 2 replies; 11+ messages in thread From: Rafael J. Wysocki @ 2010-03-04 19:49 UTC (permalink / raw) To: Shaohua Li; +Cc: H. Peter Anvin, linux-kernel, mingo, colin.king On Thursday 04 March 2010, Shaohua Li wrote: > On Thu, Mar 04, 2010 at 10:30:02AM +0800, H. Peter Anvin wrote: > > On 03/03/2010 05:23 PM, Shaohua Li wrote: > > > Colin reported a strange oops in S4 resume code path (see below). The test > > > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > > > The oops always happen a virtual address 0xc03ff000, which is mapped to the > > > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > > > > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > > > EIP is at copy_loop+0xe/0x15 > > > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > > > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > > > ... > > > ... > > > CR2: 00000000c03ff000 > > > > > > Tested-by: Colin Ian King <colin.king@canonical.com> > > > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > > --- > > > arch/x86/power/hibernate_asm_32.S | 11 +++++++++++ > > > 1 files changed, 11 insertions(+), 0 deletions(-) > > > > > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > > > index b641388..9e4ef64 100644 > > > --- a/arch/x86/power/hibernate_asm_32.S > > > +++ b/arch/x86/power/hibernate_asm_32.S > > > @@ -27,10 +27,21 @@ ENTRY(swsusp_arch_suspend) > > > ret > > > > > > ENTRY(restore_image) > > > + movl mmu_cr4_features, %ecx > > > movl resume_pg_dir, %eax > > > subl $__PAGE_OFFSET, %eax > > > movl %eax, %cr3 > > > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > > + movl %ecx, %edx > > > + andl $~(X86_CR4_PGE), %edx > > > + movl %edx, %cr4; # turn off PGE > > > +1: > > > + movl %cr3, %eax; # flush TLB > > > + movl %eax, %cr3 > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > > + movl %ecx, %cr4; # turn PGE back on > > > +1: > > > movl restore_pblist, %edx > > > .p2align 4,,7 > > > > > > > Since we're about to do another global page flush a bit further down in > > the same code, why not just leave PGE off until then? > sure, updated patch. > > > i386: do a global tlb flush in S4 resume > > Colin reported a strange oops in S4 resume code path (see below). The test > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > The oops always happen a virtual address 0xc03ff000, which is mapped to the > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > EIP is at copy_loop+0xe/0x15 > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > ... > ... > CR2: 00000000c03ff000 > > Tested-by: Colin Ian King <colin.king@canonical.com> > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > index b641388..cd5e878 100644 > --- a/arch/x86/power/hibernate_asm_32.S > +++ b/arch/x86/power/hibernate_asm_32.S > @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) > ret > > ENTRY(restore_image) > + movl mmu_cr4_features, %ecx > movl resume_pg_dir, %eax > subl $__PAGE_OFFSET, %eax > movl %eax, %cr3 > > + jecxz 1f # cr4 Pentium and higher, skip if zero > + andl $~(X86_CR4_PGE), %ecx > + movl %ecx, %cr4; # turn off PGE > + movl %cr3, %eax; # flush TLB > + movl %eax, %cr3 > +1: > movl restore_pblist, %edx > .p2align 4,,7 In that case please also remove the turning GPE off down the road. Rafael ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] i386: do a global tlb flush in S4 resume 2010-03-04 19:49 ` Rafael J. Wysocki @ 2010-03-04 20:11 ` Rafael J. Wysocki 2010-03-05 0:59 ` Shaohua Li 1 sibling, 0 replies; 11+ messages in thread From: Rafael J. Wysocki @ 2010-03-04 20:11 UTC (permalink / raw) To: Shaohua Li; +Cc: H. Peter Anvin, linux-kernel, mingo, colin.king On Thursday 04 March 2010, Rafael J. Wysocki wrote: > On Thursday 04 March 2010, Shaohua Li wrote: > > On Thu, Mar 04, 2010 at 10:30:02AM +0800, H. Peter Anvin wrote: > > > On 03/03/2010 05:23 PM, Shaohua Li wrote: > > > > Colin reported a strange oops in S4 resume code path (see below). The test > > > > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > > > > The oops always happen a virtual address 0xc03ff000, which is mapped to the > > > > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > > > > > > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > > > > EIP is at copy_loop+0xe/0x15 > > > > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > > > > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > > > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > > > > ... > > > > ... > > > > CR2: 00000000c03ff000 > > > > > > > > Tested-by: Colin Ian King <colin.king@canonical.com> > > > > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > > > --- > > > > arch/x86/power/hibernate_asm_32.S | 11 +++++++++++ > > > > 1 files changed, 11 insertions(+), 0 deletions(-) > > > > > > > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > > > > index b641388..9e4ef64 100644 > > > > --- a/arch/x86/power/hibernate_asm_32.S > > > > +++ b/arch/x86/power/hibernate_asm_32.S > > > > @@ -27,10 +27,21 @@ ENTRY(swsusp_arch_suspend) > > > > ret > > > > > > > > ENTRY(restore_image) > > > > + movl mmu_cr4_features, %ecx > > > > movl resume_pg_dir, %eax > > > > subl $__PAGE_OFFSET, %eax > > > > movl %eax, %cr3 > > > > > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > > > + movl %ecx, %edx > > > > + andl $~(X86_CR4_PGE), %edx > > > > + movl %edx, %cr4; # turn off PGE > > > > +1: > > > > + movl %cr3, %eax; # flush TLB > > > > + movl %eax, %cr3 > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > > > + movl %ecx, %cr4; # turn PGE back on > > > > +1: > > > > movl restore_pblist, %edx > > > > .p2align 4,,7 > > > > > > > > > > Since we're about to do another global page flush a bit further down in > > > the same code, why not just leave PGE off until then? > > sure, updated patch. > > > > > > i386: do a global tlb flush in S4 resume > > > > Colin reported a strange oops in S4 resume code path (see below). The test > > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > > The oops always happen a virtual address 0xc03ff000, which is mapped to the > > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > > EIP is at copy_loop+0xe/0x15 > > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > > ... > > ... > > CR2: 00000000c03ff000 > > > > Tested-by: Colin Ian King <colin.king@canonical.com> > > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > > index b641388..cd5e878 100644 > > --- a/arch/x86/power/hibernate_asm_32.S > > +++ b/arch/x86/power/hibernate_asm_32.S > > @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) > > ret > > > > ENTRY(restore_image) > > + movl mmu_cr4_features, %ecx > > movl resume_pg_dir, %eax > > subl $__PAGE_OFFSET, %eax > > movl %eax, %cr3 > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > + andl $~(X86_CR4_PGE), %ecx > > + movl %ecx, %cr4; # turn off PGE > > + movl %cr3, %eax; # flush TLB > > + movl %eax, %cr3 > > +1: > > movl restore_pblist, %edx > > .p2align 4,,7 > > In that case please also remove the turning GPE off down the road. s/GPE/PGE/ doh, too much ACPI programming lately. Rafael ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] i386: do a global tlb flush in S4 resume 2010-03-04 19:49 ` Rafael J. Wysocki 2010-03-04 20:11 ` Rafael J. Wysocki @ 2010-03-05 0:59 ` Shaohua Li 2010-03-05 20:55 ` Rafael J. Wysocki ` (2 more replies) 1 sibling, 3 replies; 11+ messages in thread From: Shaohua Li @ 2010-03-05 0:59 UTC (permalink / raw) To: Rafael J. Wysocki; +Cc: H. Peter Anvin, linux-kernel, mingo, colin.king On Fri, Mar 05, 2010 at 03:49:46AM +0800, Rafael J. Wysocki wrote: > On Thursday 04 March 2010, Shaohua Li wrote: > > On Thu, Mar 04, 2010 at 10:30:02AM +0800, H. Peter Anvin wrote: > > > On 03/03/2010 05:23 PM, Shaohua Li wrote: > > > > Colin reported a strange oops in S4 resume code path (see below). The test > > > > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > > > > The oops always happen a virtual address 0xc03ff000, which is mapped to the > > > > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > > > > > > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > > > > EIP is at copy_loop+0xe/0x15 > > > > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > > > > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > > > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > > > > ... > > > > ... > > > > CR2: 00000000c03ff000 > > > > > > > > Tested-by: Colin Ian King <colin.king@canonical.com> > > > > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > > > --- > > > > arch/x86/power/hibernate_asm_32.S | 11 +++++++++++ > > > > 1 files changed, 11 insertions(+), 0 deletions(-) > > > > > > > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > > > > index b641388..9e4ef64 100644 > > > > --- a/arch/x86/power/hibernate_asm_32.S > > > > +++ b/arch/x86/power/hibernate_asm_32.S > > > > @@ -27,10 +27,21 @@ ENTRY(swsusp_arch_suspend) > > > > ret > > > > > > > > ENTRY(restore_image) > > > > + movl mmu_cr4_features, %ecx > > > > movl resume_pg_dir, %eax > > > > subl $__PAGE_OFFSET, %eax > > > > movl %eax, %cr3 > > > > > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > > > + movl %ecx, %edx > > > > + andl $~(X86_CR4_PGE), %edx > > > > + movl %edx, %cr4; # turn off PGE > > > > +1: > > > > + movl %cr3, %eax; # flush TLB > > > > + movl %eax, %cr3 > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > > > + movl %ecx, %cr4; # turn PGE back on > > > > +1: > > > > movl restore_pblist, %edx > > > > .p2align 4,,7 > > > > > > > > > > Since we're about to do another global page flush a bit further down in > > > the same code, why not just leave PGE off until then? > > sure, updated patch. > > > > > > i386: do a global tlb flush in S4 resume > > > > Colin reported a strange oops in S4 resume code path (see below). The test > > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > > The oops always happen a virtual address 0xc03ff000, which is mapped to the > > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > > EIP is at copy_loop+0xe/0x15 > > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > > ... > > ... > > CR2: 00000000c03ff000 > > > > Tested-by: Colin Ian King <colin.king@canonical.com> > > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > > index b641388..cd5e878 100644 > > --- a/arch/x86/power/hibernate_asm_32.S > > +++ b/arch/x86/power/hibernate_asm_32.S > > @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) > > ret > > > > ENTRY(restore_image) > > + movl mmu_cr4_features, %ecx > > movl resume_pg_dir, %eax > > subl $__PAGE_OFFSET, %eax > > movl %eax, %cr3 > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > + andl $~(X86_CR4_PGE), %ecx > > + movl %ecx, %cr4; # turn off PGE > > + movl %cr3, %eax; # flush TLB > > + movl %eax, %cr3 > > +1: > > movl restore_pblist, %edx > > .p2align 4,,7 > > In that case please also remove the turning GPE off down the road. i386: do a global tlb flush in S4 resume Colin reported a strange oops in S4 resume code path (see below). The test system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. The oops always happen a virtual address 0xc03ff000, which is mapped to the last 4k of first 4M memory. Doing a global tlb flush fixes the issue. EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 EIP is at copy_loop+0xe/0x15 EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 ... ... CR2: 00000000c03ff000 Tested-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Shaohua Li <shaohua.li@intel.com> diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S index b641388..ad47dae 100644 --- a/arch/x86/power/hibernate_asm_32.S +++ b/arch/x86/power/hibernate_asm_32.S @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) ret ENTRY(restore_image) + movl mmu_cr4_features, %ecx movl resume_pg_dir, %eax subl $__PAGE_OFFSET, %eax movl %eax, %cr3 + jecxz 1f # cr4 Pentium and higher, skip if zero + andl $~(X86_CR4_PGE), %ecx + movl %ecx, %cr4; # turn off PGE + movl %cr3, %eax; # flush TLB + movl %eax, %cr3 +1: movl restore_pblist, %edx .p2align 4,,7 @@ -54,16 +61,8 @@ done: movl $swapper_pg_dir, %eax subl $__PAGE_OFFSET, %eax movl %eax, %cr3 - /* Flush TLB, including "global" things (vmalloc) */ movl mmu_cr4_features, %ecx jecxz 1f # cr4 Pentium and higher, skip if zero - movl %ecx, %edx - andl $~(X86_CR4_PGE), %edx - movl %edx, %cr4; # turn off PGE -1: - movl %cr3, %eax; # flush TLB - movl %eax, %cr3 - jecxz 1f # cr4 Pentium and higher, skip if zero movl %ecx, %cr4; # turn PGE back on 1: ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] i386: do a global tlb flush in S4 resume 2010-03-05 0:59 ` Shaohua Li @ 2010-03-05 20:55 ` Rafael J. Wysocki 2010-03-06 21:54 ` Rafael J. Wysocki 2010-03-30 18:42 ` [tip:x86/urgent] x86-32, resume: " tip-bot for Shaohua Li 2010-03-30 18:48 ` tip-bot for Shaohua Li 2 siblings, 1 reply; 11+ messages in thread From: Rafael J. Wysocki @ 2010-03-05 20:55 UTC (permalink / raw) To: Shaohua Li; +Cc: H. Peter Anvin, linux-kernel, mingo, colin.king On Friday 05 March 2010, Shaohua Li wrote: > On Fri, Mar 05, 2010 at 03:49:46AM +0800, Rafael J. Wysocki wrote: > > On Thursday 04 March 2010, Shaohua Li wrote: ... > > > > In that case please also remove the turning GPE off down the road. > > i386: do a global tlb flush in S4 resume > > Colin reported a strange oops in S4 resume code path (see below). The test > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > The oops always happen a virtual address 0xc03ff000, which is mapped to the > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > EIP is at copy_loop+0xe/0x15 > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > ... > ... > CR2: 00000000c03ff000 > > Tested-by: Colin Ian King <colin.king@canonical.com> > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > index b641388..ad47dae 100644 > --- a/arch/x86/power/hibernate_asm_32.S > +++ b/arch/x86/power/hibernate_asm_32.S > @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) > ret > > ENTRY(restore_image) > + movl mmu_cr4_features, %ecx > movl resume_pg_dir, %eax > subl $__PAGE_OFFSET, %eax > movl %eax, %cr3 > > + jecxz 1f # cr4 Pentium and higher, skip if zero > + andl $~(X86_CR4_PGE), %ecx > + movl %ecx, %cr4; # turn off PGE > + movl %cr3, %eax; # flush TLB > + movl %eax, %cr3 > +1: > movl restore_pblist, %edx > .p2align 4,,7 > > @@ -54,16 +61,8 @@ done: > movl $swapper_pg_dir, %eax > subl $__PAGE_OFFSET, %eax > movl %eax, %cr3 > - /* Flush TLB, including "global" things (vmalloc) */ > movl mmu_cr4_features, %ecx > jecxz 1f # cr4 Pentium and higher, skip if zero > - movl %ecx, %edx > - andl $~(X86_CR4_PGE), %edx > - movl %edx, %cr4; # turn off PGE > -1: > - movl %cr3, %eax; # flush TLB > - movl %eax, %cr3 Now that's too much removed. We actually _want_ to do the TLB flush here, but not unset PGE, because it's been unset already. So, the above two lines should not be removed. Also, I'd remove the first jecxz and keep the second one. > - jecxz 1f # cr4 Pentium and higher, skip if zero > movl %ecx, %cr4; # turn PGE back on > 1: Rafael ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] i386: do a global tlb flush in S4 resume 2010-03-05 20:55 ` Rafael J. Wysocki @ 2010-03-06 21:54 ` Rafael J. Wysocki 2010-03-06 23:17 ` H. Peter Anvin 0 siblings, 1 reply; 11+ messages in thread From: Rafael J. Wysocki @ 2010-03-06 21:54 UTC (permalink / raw) To: Shaohua Li, H. Peter Anvin; +Cc: linux-kernel, mingo, colin.king On Friday 05 March 2010, Rafael J. Wysocki wrote: > On Friday 05 March 2010, Shaohua Li wrote: > > On Fri, Mar 05, 2010 at 03:49:46AM +0800, Rafael J. Wysocki wrote: > > > On Thursday 04 March 2010, Shaohua Li wrote: > ... > > > > > > In that case please also remove the turning GPE off down the road. > > > > i386: do a global tlb flush in S4 resume > > > > Colin reported a strange oops in S4 resume code path (see below). The test > > system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. > > The oops always happen a virtual address 0xc03ff000, which is mapped to the > > last 4k of first 4M memory. Doing a global tlb flush fixes the issue. > > > > EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 > > EIP is at copy_loop+0xe/0x15 > > EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c > > ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 > > DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 > > ... > > ... > > CR2: 00000000c03ff000 > > > > Tested-by: Colin Ian King <colin.king@canonical.com> > > Signed-off-by: Shaohua Li <shaohua.li@intel.com> > > > > diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S > > index b641388..ad47dae 100644 > > --- a/arch/x86/power/hibernate_asm_32.S > > +++ b/arch/x86/power/hibernate_asm_32.S > > @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) > > ret > > > > ENTRY(restore_image) > > + movl mmu_cr4_features, %ecx > > movl resume_pg_dir, %eax > > subl $__PAGE_OFFSET, %eax > > movl %eax, %cr3 > > > > + jecxz 1f # cr4 Pentium and higher, skip if zero > > + andl $~(X86_CR4_PGE), %ecx > > + movl %ecx, %cr4; # turn off PGE > > + movl %cr3, %eax; # flush TLB > > + movl %eax, %cr3 > > +1: > > movl restore_pblist, %edx > > .p2align 4,,7 > > > > @@ -54,16 +61,8 @@ done: > > movl $swapper_pg_dir, %eax > > subl $__PAGE_OFFSET, %eax > > movl %eax, %cr3 > > - /* Flush TLB, including "global" things (vmalloc) */ > > movl mmu_cr4_features, %ecx > > jecxz 1f # cr4 Pentium and higher, skip if zero > > - movl %ecx, %edx > > - andl $~(X86_CR4_PGE), %edx > > - movl %edx, %cr4; # turn off PGE > > -1: > > - movl %cr3, %eax; # flush TLB > > - movl %eax, %cr3 > > Now that's too much removed. We actually _want_ to do the TLB flush here, > but not unset PGE, because it's been unset already. > > So, the above two lines should not be removed. > > Also, I'd remove the first jecxz and keep the second one. Scratch that, the patch is fine, because we load cr3 right before that. Sorry for the noise. Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Peter, are you going to take it or should I handle it? Rafael ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] i386: do a global tlb flush in S4 resume 2010-03-06 21:54 ` Rafael J. Wysocki @ 2010-03-06 23:17 ` H. Peter Anvin 0 siblings, 0 replies; 11+ messages in thread From: H. Peter Anvin @ 2010-03-06 23:17 UTC (permalink / raw) To: Rafael J. Wysocki; +Cc: Shaohua Li, linux-kernel, mingo, colin.king On 03/06/2010 01:54 PM, Rafael J. Wysocki wrote: > > Peter, are you going to take it or should I handle it? > I'll take it after -rc1. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [tip:x86/urgent] x86-32, resume: do a global tlb flush in S4 resume 2010-03-05 0:59 ` Shaohua Li 2010-03-05 20:55 ` Rafael J. Wysocki @ 2010-03-30 18:42 ` tip-bot for Shaohua Li 2010-03-30 18:48 ` tip-bot for Shaohua Li 2 siblings, 0 replies; 11+ messages in thread From: tip-bot for Shaohua Li @ 2010-03-30 18:42 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hpa, mingo, colin.king, shaohua.li, tglx, rjw Commit-ID: f1ddc38590a400e19ba67963dac5bc3addc6e14b Gitweb: http://git.kernel.org/tip/f1ddc38590a400e19ba67963dac5bc3addc6e14b Author: Shaohua Li <shaohua.li@intel.com> AuthorDate: Fri, 5 Mar 2010 08:59:32 +0800 Committer: H. Peter Anvin <hpa@zytor.com> CommitDate: Tue, 30 Mar 2010 10:50:42 -0700 x86-32, resume: do a global tlb flush in S4 resume Colin King reported a strange oops in S4 resume code path (see below). The test system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. The oops always happen a virtual address 0xc03ff000, which is mapped to the last 4k of first 4M memory. Doing a global tlb flush fixes the issue. EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 EIP is at copy_loop+0xe/0x15 EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 ... ... CR2: 00000000c03ff000 Tested-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Shaohua Li <shaohua.li@intel.com> LKML-Reference: <20100305005932.GA22675@sli10-desk.sh.intel.com> Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: H. Peter Anvin <hpa@zytor.com> --- arch/x86/power/hibernate_asm_32.S | 15 +++++++-------- 1 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S index b641388..ad47dae 100644 --- a/arch/x86/power/hibernate_asm_32.S +++ b/arch/x86/power/hibernate_asm_32.S @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) ret ENTRY(restore_image) + movl mmu_cr4_features, %ecx movl resume_pg_dir, %eax subl $__PAGE_OFFSET, %eax movl %eax, %cr3 + jecxz 1f # cr4 Pentium and higher, skip if zero + andl $~(X86_CR4_PGE), %ecx + movl %ecx, %cr4; # turn off PGE + movl %cr3, %eax; # flush TLB + movl %eax, %cr3 +1: movl restore_pblist, %edx .p2align 4,,7 @@ -54,16 +61,8 @@ done: movl $swapper_pg_dir, %eax subl $__PAGE_OFFSET, %eax movl %eax, %cr3 - /* Flush TLB, including "global" things (vmalloc) */ movl mmu_cr4_features, %ecx jecxz 1f # cr4 Pentium and higher, skip if zero - movl %ecx, %edx - andl $~(X86_CR4_PGE), %edx - movl %edx, %cr4; # turn off PGE -1: - movl %cr3, %eax; # flush TLB - movl %eax, %cr3 - jecxz 1f # cr4 Pentium and higher, skip if zero movl %ecx, %cr4; # turn PGE back on 1: ^ permalink raw reply [flat|nested] 11+ messages in thread
* [tip:x86/urgent] x86-32, resume: do a global tlb flush in S4 resume 2010-03-05 0:59 ` Shaohua Li 2010-03-05 20:55 ` Rafael J. Wysocki 2010-03-30 18:42 ` [tip:x86/urgent] x86-32, resume: " tip-bot for Shaohua Li @ 2010-03-30 18:48 ` tip-bot for Shaohua Li 2 siblings, 0 replies; 11+ messages in thread From: tip-bot for Shaohua Li @ 2010-03-30 18:48 UTC (permalink / raw) To: linux-tip-commits Cc: linux-kernel, hpa, mingo, stable, colin.king, shaohua.li, tglx, rjw Commit-ID: 8ae06d223f8203c72104e5c0c4ee49a000aedb42 Gitweb: http://git.kernel.org/tip/8ae06d223f8203c72104e5c0c4ee49a000aedb42 Author: Shaohua Li <shaohua.li@intel.com> AuthorDate: Fri, 5 Mar 2010 08:59:32 +0800 Committer: H. Peter Anvin <hpa@zytor.com> CommitDate: Tue, 30 Mar 2010 11:46:02 -0700 x86-32, resume: do a global tlb flush in S4 resume Colin King reported a strange oops in S4 resume code path (see below). The test system has i5/i7 CPU. The kernel doesn't open PAE, so 4M page table is used. The oops always happen a virtual address 0xc03ff000, which is mapped to the last 4k of first 4M memory. Doing a global tlb flush fixes the issue. EIP: 0060:[<c0493a01>] EFLAGS: 00010086 CPU: 0 EIP is at copy_loop+0xe/0x15 EAX: 36aeb000 EBX: 00000000 ECX: 00000400 EDX: f55ad46c ESI: 0f800000 EDI: c03ff000 EBP: f67fbec4 ESP: f67fbea8 DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 ... ... CR2: 00000000c03ff000 Tested-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Shaohua Li <shaohua.li@intel.com> LKML-Reference: <20100305005932.GA22675@sli10-desk.sh.intel.com> Acked-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: <stable@kernel.org> --- arch/x86/power/hibernate_asm_32.S | 15 +++++++-------- 1 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/x86/power/hibernate_asm_32.S b/arch/x86/power/hibernate_asm_32.S index b641388..ad47dae 100644 --- a/arch/x86/power/hibernate_asm_32.S +++ b/arch/x86/power/hibernate_asm_32.S @@ -27,10 +27,17 @@ ENTRY(swsusp_arch_suspend) ret ENTRY(restore_image) + movl mmu_cr4_features, %ecx movl resume_pg_dir, %eax subl $__PAGE_OFFSET, %eax movl %eax, %cr3 + jecxz 1f # cr4 Pentium and higher, skip if zero + andl $~(X86_CR4_PGE), %ecx + movl %ecx, %cr4; # turn off PGE + movl %cr3, %eax; # flush TLB + movl %eax, %cr3 +1: movl restore_pblist, %edx .p2align 4,,7 @@ -54,16 +61,8 @@ done: movl $swapper_pg_dir, %eax subl $__PAGE_OFFSET, %eax movl %eax, %cr3 - /* Flush TLB, including "global" things (vmalloc) */ movl mmu_cr4_features, %ecx jecxz 1f # cr4 Pentium and higher, skip if zero - movl %ecx, %edx - andl $~(X86_CR4_PGE), %edx - movl %edx, %cr4; # turn off PGE -1: - movl %cr3, %eax; # flush TLB - movl %eax, %cr3 - jecxz 1f # cr4 Pentium and higher, skip if zero movl %ecx, %cr4; # turn PGE back on 1: ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2010-03-30 18:49 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2010-03-04 1:23 [PATCH] i386: do a global tlb flush in S4 resume Shaohua Li 2010-03-04 2:30 ` H. Peter Anvin 2010-03-04 2:41 ` Shaohua Li 2010-03-04 19:49 ` Rafael J. Wysocki 2010-03-04 20:11 ` Rafael J. Wysocki 2010-03-05 0:59 ` Shaohua Li 2010-03-05 20:55 ` Rafael J. Wysocki 2010-03-06 21:54 ` Rafael J. Wysocki 2010-03-06 23:17 ` H. Peter Anvin 2010-03-30 18:42 ` [tip:x86/urgent] x86-32, resume: " tip-bot for Shaohua Li 2010-03-30 18:48 ` tip-bot for Shaohua Li
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