* [tip:perf/urgent] tools arch x86: Sync asm/cpufeatures.h with the kernel sources
@ 2019-03-29 20:38 tip-bot for Arnaldo Carvalho de Melo
0 siblings, 0 replies; 5+ messages in thread
From: tip-bot for Arnaldo Carvalho de Melo @ 2019-03-29 20:38 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, peterz, jolsa, tglx, hpa, adrian.hunter, mingo,
acme, namhyung
Commit-ID: 949af89af02c2d66db973c5bca01b7858e1ce0ba
Gitweb: https://git.kernel.org/tip/949af89af02c2d66db973c5bca01b7858e1ce0ba
Author: Arnaldo Carvalho de Melo <acme@redhat.com>
AuthorDate: Mon, 25 Mar 2019 14:25:33 -0300
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitDate: Thu, 28 Mar 2019 14:31:56 -0300
tools arch x86: Sync asm/cpufeatures.h with the kernel sources
To get the changes from:
52f64909409c ("x86: Add TSX Force Abort CPUID/MSR")
That don't cause any changes in the generated perf binaries.
And silence this perf build warning:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/n/tip-zv8kw8vnb1zppflncpwfsv2w@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 6d6122524711..981ff9479648 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -344,6 +344,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
^ permalink raw reply [flat|nested] 5+ messages in thread[parent not found: <tip-pq63abgknsaeov23p80d8gjv@git.kernel.org>]
* [tip: perf/urgent] tools arch x86: Sync asm/cpufeatures.h with the kernel sources
[not found] <tip-pq63abgknsaeov23p80d8gjv@git.kernel.org>
@ 2019-09-22 10:52 ` tip-bot2 for Arnaldo Carvalho de Melo
0 siblings, 0 replies; 5+ messages in thread
From: tip-bot2 for Arnaldo Carvalho de Melo @ 2019-09-22 10:52 UTC (permalink / raw)
To: linux-tip-commits
Cc: Adrian Hunter, Borislav Petkov, Gayatri Kammela, Jiri Olsa,
Josh Poimboeuf, Namhyung Kim, Thomas Gleixner, Thomas Hellstrom,
Arnaldo Carvalho de Melo, Ingo Molnar, Borislav Petkov,
linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 40f1c039c7c6de913ee04eac585102e2fce7f6f7
Gitweb: https://git.kernel.org/tip/40f1c039c7c6de913ee04eac585102e2fce7f6f7
Author: Arnaldo Carvalho de Melo <acme@redhat.com>
AuthorDate: Fri, 20 Sep 2019 15:00:49 -03:00
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitterDate: Fri, 20 Sep 2019 15:00:49 -03:00
tools arch x86: Sync asm/cpufeatures.h with the kernel sources
To pick up the changes from:
b4dd4f6e3648 ("x86/vmware: Add a header file for hypercall definitions")
f36cf386e3fe ("x86/speculation/swapgs: Exclude ATOMs from speculation through SWAPGS")
be261ffce6f1 ("x86: Remove X86_FEATURE_MFENCE_RDTSC")
018ebca8bd70 ("x86/cpufeatures: Enable a new AVX512 CPU feature")
These don't cause any changes in tooling, just silences this perf build
warning:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
To clarify, updating those files cause these bits of tools/perf to rebuild:
CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o
INSTALL GTK UI
LD /tmp/build/perf/bench/perf-in.o
Those use just:
$ grep FEATURE tools/arch/x86/lib/mem*.S
tools/arch/x86/lib/memcpy_64.S: ALTERNATIVE_2 "jmp memcpy_orig", "", X86_FEATURE_REP_GOOD, \
tools/arch/x86/lib/memcpy_64.S: "jmp memcpy_erms", X86_FEATURE_ERMS
tools/arch/x86/lib/memset_64.S: ALTERNATIVE_2 "jmp memset_orig", "", X86_FEATURE_REP_GOOD, \
tools/arch/x86/lib/memset_64.S: "jmp memset_erms", X86_FEATURE_ERMS
$
I.e. none of the feature defines added/removed by the patches above.
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Gayatri Kammela <gayatri.kammela@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Thomas Hellstrom <thellstrom@vmware.com>
Link: https://lkml.kernel.org/n/tip-pq63abgknsaeov23p80d8gjv@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/arch/x86/include/asm/cpufeatures.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 5171b9c..0652d3e 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -231,6 +231,8 @@
#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer VMMCALL to VMCALL */
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
#define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */
+#define X86_FEATURE_VMCALL ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
+#define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
@@ -354,6 +356,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <tip-yufg9yt2nbkh45r9xvxnnscq@git.kernel.org>]
* [tip: perf/urgent] tools arch x86: Sync asm/cpufeatures.h with the kernel sources
[not found] <tip-yufg9yt2nbkh45r9xvxnnscq@git.kernel.org>
@ 2019-12-04 7:53 ` tip-bot2 for Arnaldo Carvalho de Melo
0 siblings, 0 replies; 5+ messages in thread
From: tip-bot2 for Arnaldo Carvalho de Melo @ 2019-12-04 7:53 UTC (permalink / raw)
To: linux-tip-commits
Cc: Adrian Hunter, Babu Moger, Borislav Petkov, Jiri Olsa,
Namhyung Kim, Pawan Gupta, Thomas Gleixner, Vineela Tummalapalli,
Arnaldo Carvalho de Melo, x86, LKML
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: a717ab38a51404a3f7069987f77676cde82139ac
Gitweb: https://git.kernel.org/tip/a717ab38a51404a3f7069987f77676cde82139ac
Author: Arnaldo Carvalho de Melo <acme@redhat.com>
AuthorDate: Mon, 02 Dec 2019 15:11:51 -03:00
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitterDate: Mon, 02 Dec 2019 15:20:05 -03:00
tools arch x86: Sync asm/cpufeatures.h with the kernel sources
To pick up the changes from:
a25bbc2644f0 ("Merge branches 'x86-cpu-for-linus' and 'x86-fpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip")
db4d30fbb71b ("x86/bugs: Add ITLB_MULTIHIT bug infrastructure")
1b42f017415b ("x86/speculation/taa: Add mitigation for TSX Async Abort")
9d40b85bb46a ("x86/cpufeatures: Add feature bit RDPRU on AMD")
These don't cause any changes in tooling, just silences this perf build
warning:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Babu Moger <babu.moger@amd.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vineela Tummalapalli <vineela.tummalapalli@intel.com>
Link: https://lkml.kernel.org/n/tip-yufg9yt2nbkh45r9xvxnnscq@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/arch/x86/include/asm/cpufeatures.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 0652d3e..e9b6249 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -292,6 +292,7 @@
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_RDPRU (13*32+ 4) /* Read processor register at user level */
#define X86_FEATURE_WBNOINVD (13*32+ 9) /* WBNOINVD instruction */
#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
@@ -399,5 +400,7 @@
#define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
#define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */
#define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
+#define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
+#define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
#endif /* _ASM_X86_CPUFEATURES_H */
^ permalink raw reply [flat|nested] 5+ messages in thread
* [tip: perf/urgent] tools arch x86: Sync asm/cpufeatures.h with the kernel sources
@ 2020-02-15 8:41 tip-bot2 for Arnaldo Carvalho de Melo
0 siblings, 0 replies; 5+ messages in thread
From: tip-bot2 for Arnaldo Carvalho de Melo @ 2020-02-15 8:41 UTC (permalink / raw)
To: linux-tip-commits
Cc: Adrian Hunter, Borislav Petkov, Jiri Olsa, Namhyung Kim,
Sean Christopherson, Tony Luck, Arnaldo Carvalho de Melo, x86,
LKML
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 71dd65289793df31e9f10c6b112e5e32dfd89c1d
Gitweb: https://git.kernel.org/tip/71dd65289793df31e9f10c6b112e5e32dfd89c1d
Author: Arnaldo Carvalho de Melo <acme@redhat.com>
AuthorDate: Wed, 12 Feb 2020 12:33:34 -03:00
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitterDate: Wed, 12 Feb 2020 12:33:34 -03:00
tools arch x86: Sync asm/cpufeatures.h with the kernel sources
To pick up the changes from:
85c17291e2eb ("x86/cpufeatures: Add flag to track whether MSR IA32_FEAT_CTL is configured")
f444a5ff95dc ("x86/cpufeatures: Add support for fast short REP; MOVSB")
These don't cause any changes in tooling, just silences this perf build
warning:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Sean Christopherson <sean.j.christopherson@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/arch/x86/include/asm/cpufeatures.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index e9b6249..f3327cb 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -220,6 +220,7 @@
#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
+#define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
/* Virtualization flags: Linux defined, word 8 */
#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
@@ -357,6 +358,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
+#define X86_FEATURE_FSRM (18*32+ 4) /* Fast Short Rep Mov */
#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
^ permalink raw reply [flat|nested] 5+ messages in thread* [tip: perf/urgent] tools arch x86: Sync asm/cpufeatures.h with the kernel sources
@ 2020-04-16 8:31 tip-bot2 for Arnaldo Carvalho de Melo
0 siblings, 0 replies; 5+ messages in thread
From: tip-bot2 for Arnaldo Carvalho de Melo @ 2020-04-16 8:31 UTC (permalink / raw)
To: linux-tip-commits
Cc: Adrian Hunter, Jiri Olsa, Namhyung Kim, Borislav Petkov,
Kim Phillips, Peter Zijlstra (Intel),
Wei Huang, Arnaldo Carvalho de Melo, x86, LKML
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: e00a2d907ec9bf0e8a46543857f25ce95980c341
Gitweb: https://git.kernel.org/tip/e00a2d907ec9bf0e8a46543857f25ce95980c341
Author: Arnaldo Carvalho de Melo <acme@redhat.com>
AuthorDate: Tue, 14 Apr 2020 09:08:23 -03:00
Committer: Arnaldo Carvalho de Melo <acme@redhat.com>
CommitterDate: Tue, 14 Apr 2020 09:08:23 -03:00
tools arch x86: Sync asm/cpufeatures.h with the kernel sources
To pick up the changes from:
077168e241ec ("x86/mce/amd: Add PPIN support for AMD MCE")
753039ef8b2f ("x86/cpu/amd: Call init_amd_zn() om Family 19h processors too")
6650cdd9a8cc ("x86/split_lock: Enable split lock detection by kernel")
These don't cause any changes in tooling, just silences this perf build
warning:
Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Borislav Petkov <bp@suse.de>
Cc: Kim Phillips <kim.phillips@amd.com>
Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/arch/x86/include/asm/cpufeatures.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index f3327cb..db18994 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -217,7 +217,7 @@
#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
-#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
+#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 or above (Zen) */
#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
#define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
@@ -285,6 +285,7 @@
#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
#define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
+#define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
@@ -299,6 +300,7 @@
#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
+#define X86_FEATURE_AMD_PPIN (13*32+23) /* Protected Processor Inventory Number */
#define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */
#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
#define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
@@ -367,6 +369,7 @@
#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
+#define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
/*
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-16 9:12 UTC | newest]
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2019-03-29 20:38 [tip:perf/urgent] tools arch x86: Sync asm/cpufeatures.h with the kernel sources tip-bot for Arnaldo Carvalho de Melo
[not found] <tip-pq63abgknsaeov23p80d8gjv@git.kernel.org>
2019-09-22 10:52 ` [tip: perf/urgent] " tip-bot2 for Arnaldo Carvalho de Melo
[not found] <tip-yufg9yt2nbkh45r9xvxnnscq@git.kernel.org>
2019-12-04 7:53 ` tip-bot2 for Arnaldo Carvalho de Melo
2020-02-15 8:41 tip-bot2 for Arnaldo Carvalho de Melo
2020-04-16 8:31 tip-bot2 for Arnaldo Carvalho de Melo
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