From: Krzysztof Kozlowski <krzk@kernel.org>
To: Xianwei Zhao <xianwei.zhao@amlogic.com>
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Liang Yang <liang.yang@amlogic.com>,
Feng Chen <feng.chen@amlogic.com>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org
Subject: Re: [PATCH 1/3] spi: dt-bindings: add doc for Amlogic A113L2 SFC
Date: Wed, 13 Aug 2025 18:19:34 +0200 [thread overview]
Message-ID: <017a4d15-286d-4e0a-89ff-f658009a6de6@kernel.org> (raw)
In-Reply-To: <d872a711-7442-4e2e-bc59-0d6f4f656fde@amlogic.com>
On 13/08/2025 11:34, Xianwei Zhao wrote:
> Hi Krzysztof,
> Thanks for your reply.
>
> On 2025/8/13 15:36, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On 13/08/2025 08:13, Xianwei Zhao wrote:
>>>>> +allOf:
>>>>> + - $ref: /schemas/spi/spi-controller.yaml#
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + const: amlogic,a4-spifc
>>>>> +
>>>>> + reg:
>>>>> + items:
>>>>> + - description: core registers
>>>>> + - description: parent clk control registers
>>>>
>>>> Why are you poking to parent node or to clock registers? This looks like
>>>> mixing up device address spaces.
>>>>
>>>
>>> The SPIFC bus clock multiplexes EMMC modules, so the corresponding
>>> frequency division register is also in EMMC module. The SPIFC and the
>>> EMMC modules cannot be used simultaneously.
>>
>> Then obviously you cannot put here EMMC or parent registers.
>>
>> It looks really like you miss proper hardware representation.
>>
>
> It does seem a bit unusual. However, in our hardware design, EMMC and
> SFC modules are integrated, and they share common resources such as the
> clock and I/O pins .They are mutually exclusive.
>
How did you express it in DT? This looks similar to serial engines and
such are not implemented independently.
> Here, I'll modify the register description. Do you think it's feasible
No, because it changes nothing... Clock provider pokes clock divider
registers. Not clock consumer.
Best regards,
Krzysztof
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next prev parent reply other threads:[~2025-08-13 18:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-08 2:00 [PATCH 0/3] support for Amlogic SPI Flash Controller IP Xianwei Zhao via B4 Relay
2025-08-08 2:00 ` [PATCH 1/3] spi: dt-bindings: add doc for Amlogic A113L2 SFC Xianwei Zhao via B4 Relay
2025-08-08 8:03 ` Krzysztof Kozlowski
2025-08-13 6:13 ` Xianwei Zhao
2025-08-13 7:36 ` Krzysztof Kozlowski
2025-08-13 9:34 ` Xianwei Zhao
2025-08-13 16:19 ` Krzysztof Kozlowski [this message]
2025-08-14 6:38 ` Xianwei Zhao
2025-08-17 7:20 ` Krzysztof Kozlowski
2025-08-19 5:32 ` Xianwei Zhao
2025-08-08 2:00 ` [PATCH 2/3] spi: amlogic: add driver for Amlogic SPI Flash Controller Xianwei Zhao via B4 Relay
2025-08-08 2:00 ` [PATCH 3/3] MAINTAINERS: Add an entry for Amlogic spifc driver Xianwei Zhao via B4 Relay
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