Re: [PATCH 1/3] spi: dt-bindings: add doc for Amlogic A113L2 SFC

[Xianwei Zhao <xianwei.zhao@amlogic.com>]

Hi Krzysztof,
    Thanks  for your reply.

On 2025/8/13 15:36, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
> 
> On 13/08/2025 08:13, Xianwei Zhao wrote:
>>>> +allOf:
>>>> +  - $ref: /schemas/spi/spi-controller.yaml#
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: amlogic,a4-spifc
>>>> +
>>>> +  reg:
>>>> +    items:
>>>> +      - description: core registers
>>>> +      - description: parent clk control registers
>>>
>>> Why are you poking to parent node or to clock registers? This looks like
>>> mixing up device address spaces.
>>>
>>
>> The SPIFC bus clock multiplexes EMMC modules, so the corresponding
>> frequency division register is also in EMMC module. The SPIFC and the
>> EMMC modules cannot be used simultaneously.
> 
> Then obviously you cannot put here EMMC or parent registers.
> 
> It looks really like you miss proper hardware representation.
> 

It does seem a bit unusual. However, in our hardware design, EMMC and 
SFC modules are integrated, and they share common resources such as the 
clock and I/O pins .They are mutually exclusive.

Here, I'll modify the register description. Do you think it's feasible

description: EMMC clock divider control

>>
>>>> +
>>>> +  reg-names:
>>>> +    items:
>>>> +      - const: core
>>>> +      - const: pclk
>>>> +
>>>> +  clocks:
>>>> +    items:
>>>> +      - description: clock gate
>>>
>>> Are you sure this is separate clock input to this device?
>>>
>>
>> This clock is used by the APB interface to access the SPIFC registers.
> 
> So APB clock?
> 

Yes. The APB clock serves as the source clock, but each device receives 
it through an individual clock gating circuit.

I will modify the description of this clock

description: apb gate

> 
> 
> Best regards,
> Krzysztof

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