From: Jerome Brunet <jbrunet@baylibre.com>
To: Jian Hu <jian.hu@amlogic.com>
Cc: sashiko-reviews@lists.linux.dev,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, robh@kernel.org,
conor+dt@kernel.org, neil.armstrong@linaro.org
Subject: Re: [PATCH RFC RFT v2 2/3] clk: divider: add CLK_DIVIDER_INVALID_ZERO flag
Date: Thu, 05 Nov 2026 14:39:56 +0100 [thread overview]
Message-ID: <179388599696.2573818.3573650064673131943.b4-reply@b4> (raw)
In-Reply-To: <02476c54-d8ae-479d-898f-cd89ee2f7c24@amlogic.com>
On 2026-11-04 17:07:10+08:00, Jian Hu wrote:
> On 10/29/2026 5:47 PM, sashiko-bot@kernel.org wrote:
>
> > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> > - [High] clk: divider: unhandled zero divisor in divider_ro_determine_rate()
> > --
> >
> > commit 5ec3118aee2f03855552c58a4a8533e035b565bc
> > Author: Jian Hu <jian.hu@amlogic.com>
> >
> > clk: divider: add CLK_DIVIDER_INVALID_ZERO flag
> >
> > This commit introduces the CLK_DIVIDER_INVALID_ZERO flag for dividers where
> > a zero divisor value represents an invalid hardware state rather than a
> > pass-through. When this flag is set and the divisor evaluates to zero,
> > divider_recalc_rate() returns 0 without emitting a warning.
> >
> > [Severity: High]
> > Should divider_ro_determine_rate() in drivers/clk/clk-divider.c also handle
> > a zero divisor when CLK_DIVIDER_INVALID_ZERO or CLK_DIVIDER_ALLOW_ZERO is
> > set?
> >
> > When a read-only divider has a register value val that maps to div == 0 via
> > _get_div() (for example, when CLK_DIVIDER_INVALID_ZERO is combined with
> > CLK_DIVIDER_ONE_BASED or an unmapped table entry alongside
> > CLK_DIVIDER_READ_ONLY), calling clk_round_rate() or clk_set_rate() invokes
> > clk_divider_determine_rate()->divider_ro_determine_rate():
> >
> > drivers/clk/clk-divider.c:divider_ro_determine_rate() {
> > int div;
> >
> > div = _get_div(table, val, flags, width);
> >
> > /* Even a read-only clock can propagate a rate change */
> > if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
> > if (!req->best_parent_hw)
> > return -EINVAL;
> >
> > req->best_parent_rate = clk_hw_round_rate(req->best_parent_hw,
> > req->rate * div);
> > }
> >
> > req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
> >
> > return 0;
> > }
> >
> > Unlike divider_recalc_rate(), divider_ro_determine_rate() does not check for
> > !div before calling DIV_ROUND_UP_ULL(), which will trigger a division by zero
> > in the kernel when div is 0.
>
> In this patch, the dividers which set CLK_DIVIDER_INVALID_ZERO use
> divider_determine_rate(),
>
> not divider_ro_determine_rate().
Yet the point raised is valid. The change must work for everyone, not just you.
--
Jerome
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next prev parent reply other threads:[~2026-11-05 13:40 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 9:30 [PATCH RFC RFT v2 0/3] clk: meson: Refactor PLL pre-divider as a divider clock Jian Hu via B4 Relay
2026-10-29 9:30 ` [PATCH RFC RFT v2 1/3] dt-bindings: clock: amlogic: Add PLL pre-divider clock IDs Jian Hu via B4 Relay
2026-10-29 9:30 ` [PATCH RFC RFT v2 2/3] clk: divider: add CLK_DIVIDER_INVALID_ZERO flag Jian Hu via B4 Relay
2026-10-29 9:47 ` sashiko-bot
2026-11-04 9:07 ` Jian Hu
2026-11-05 13:39 ` Jerome Brunet [this message]
2026-11-05 17:50 ` Jerome Brunet
2026-10-29 9:30 ` [PATCH RFC RFT v2 3/3] clk: meson: pll: Remove the dedicated n parameter Jian Hu via B4 Relay
2026-10-29 9:57 ` sashiko-bot
2026-11-04 11:59 ` Jian Hu
2026-11-05 17:50 ` Jerome Brunet
2026-11-05 17:50 ` [PATCH RFC RFT v2 0/3] clk: meson: Refactor PLL pre-divider as a divider clock Jerome Brunet
2026-11-09 8:55 ` Jian Hu
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