[PATCH 0/1] Meson8b RGMII Ethernet pin cleanup

[PATCH 0/1] Meson8b RGMII Ethernet pin cleanup

[Martin Blumenstingl]

Hi Emiliano, Hi Linus,

could you please test the patch from this series on your Odroid-C1?
I tested it on mine and Ethernet seems to be working fine with it.

There should be no functional changes with this patch as it just
removes an incorrect pad configuration for DIF_2_P and DIF_2_N for
the TXD0 and TXD1 signal (as these are routed to GPIOH_5 and GPIOH_6
on Odroid-C1).


Martin Blumenstingl (1):
  ARM: dts: meson8b: RGMII doesn't use the eth_txd1_1 and eth_txd0_1
    pins

 arch/arm/boot/dts/meson8b.dtsi | 2 --
 1 file changed, 2 deletions(-)

-- 
2.17.0

[PATCH 1/1] ARM: dts: meson8b: RGMII doesn't use the eth_txd1_1 and eth_txd0_1 pins

[Martin Blumenstingl]

The pin groups eth_txd0_0 and eth_txd0_1 are both connected to the
Ethernet controller's TXD0 data line. The only difference is that
eth_txd0_0 is routed to GPIOH_6 while eth_txd0_1 is routed to DIF_2_P.
eth_txd1_0 and eth_txd1_1 are similar: eth_txd1_0 is routed to GPIOH_5
and eth_txd1_1 is routed to DIF_2_N.

The schematics of the Odroid-C1+ show that it uses GPIOH_5 and GPIOH_6
for the TXD0 and TXD1 data lines. Thus we can drop eth_txd0_1 and
eth_txd1_1 (which are routed to DIF_2_P and DIF_2_N) from the RGMII
group.

Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Emiliano Ingrassia <ingrassia@epigenesys.com>
Cc: Linus L?ssing <linus.luessing@c0d3.blue>
---
 arch/arm/boot/dts/meson8b.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 6cfd7e225cee..5deff6819f7d 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -200,9 +200,7 @@
 				groups = "eth_tx_clk",
 					 "eth_tx_en",
 					 "eth_txd1_0",
-					 "eth_txd1_1",
 					 "eth_txd0_0",
-					 "eth_txd0_1",
 					 "eth_rx_clk",
 					 "eth_rx_dv",
 					 "eth_rxd1",
-- 
2.17.0

[PATCH 0/1] Meson8b RGMII Ethernet pin cleanup

[Martin Blumenstingl]

On Wed, May 2, 2018 at 12:00 AM, Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> Hi Emiliano, Hi Linus,
>
> could you please test the patch from this series on your Odroid-C1?
> I tested it on mine and Ethernet seems to be working fine with it.
I forgot to mention: if you want to test this with v4.17-rc3 then you
need the following patches on top of v4.17-rc3:
- clk: meson: meson8b: fix meson8b_fclk_div3_div clock name [0]
- clk: meson: meson8b: fix meson8b_cpu_clk parent clock name [1]
- clk: meson: meson8b: mark fclk_div gate clocks as CLK_IS_CRITICAL [2]

> There should be no functional changes with this patch as it just
> removes an incorrect pad configuration for DIF_2_P and DIF_2_N for
> the TXD0 and TXD1 signal (as these are routed to GPIOH_5 and GPIOH_6
> on Odroid-C1).
>
>
> Martin Blumenstingl (1):
>   ARM: dts: meson8b: RGMII doesn't use the eth_txd1_1 and eth_txd0_1
>     pins
>
>  arch/arm/boot/dts/meson8b.dtsi | 2 --
>  1 file changed, 2 deletions(-)
>
> --
> 2.17.0
>


[0] https://patchwork.kernel.org/patch/10354473/
[1] https://patchwork.kernel.org/patch/10358009/
[2] https://patchwork.kernel.org/patch/10374537/

[PATCH 0/1] Meson8b RGMII Ethernet pin cleanup

[Emiliano Ingrassia]

Hi Martin,

the patch seems to work fine but I have two questions.

First, should we remove those pins from "ethernet_groups" structure
in "drivers/pinctrl/meson/pinctrl-meson8b.c" ?

Second, following the Odroid-C1+ schematics there are two pins,
"eth_rxd2" and "eth_rxd3" which are not configured by the pin controller
driver, nor included in the pins group in the relative device tree.
Should we configure and include them ?

Thanks,

Emiliano

On Wed, May 02, 2018 at 12:00:44AM +0200, Martin Blumenstingl wrote:
> Hi Emiliano, Hi Linus,
>
> could you please test the patch from this series on your Odroid-C1?
> I tested it on mine and Ethernet seems to be working fine with it.
>
> There should be no functional changes with this patch as it just
> removes an incorrect pad configuration for DIF_2_P and DIF_2_N for
> the TXD0 and TXD1 signal (as these are routed to GPIOH_5 and GPIOH_6
> on Odroid-C1).
>
>
> Martin Blumenstingl (1):
>   ARM: dts: meson8b: RGMII doesn't use the eth_txd1_1 and eth_txd0_1
>     pins
>
>  arch/arm/boot/dts/meson8b.dtsi | 2 --
>  1 file changed, 2 deletions(-)
>
> --
> 2.17.0
>

[PATCH 0/1] Meson8b RGMII Ethernet pin cleanup

[Martin Blumenstingl]

Hi Emiliano,

On Thu, May 3, 2018 at 7:06 PM, Emiliano Ingrassia
<ingrassia@epigenesys.com> wrote:
> Hi Martin,
>
> the patch seems to work fine but I have two questions.
thank you for testing this! :)

> First, should we remove those pins from "ethernet_groups" structure
> in "drivers/pinctrl/meson/pinctrl-meson8b.c" ?
I believe that some boards with RMII (100Mbit/s) PHY use TXD0/TXD1 on
DIF_2_P and DIF_2_N
so we should keep support for these in the driver

> Second, following the Odroid-C1+ schematics there are two pins,
> "eth_rxd2" and "eth_rxd3" which are not configured by the pin controller
> driver, nor included in the pins group in the relative device tree.
> Should we configure and include them ?
interesting - good catch. I think we should include them in both, the
pinctrl driver and meson8b.dtsi
do you know which pads are used for "eth_rxd2" and "eth_rxd3"?


Regards
Martin

[PATCH 0/1] Meson8b RGMII Ethernet pin cleanup

[Emiliano Ingrassia]

Hi Martin,

On Fri, May 04, 2018 at 10:09:37PM +0200, Martin Blumenstingl wrote:
> Hi Emiliano,
> 
> On Thu, May 3, 2018 at 7:06 PM, Emiliano Ingrassia
> <ingrassia@epigenesys.com> wrote:
> > Hi Martin,
> >
> > the patch seems to work fine but I have two questions.
> thank you for testing this! :)
>

Thanks for your patch! :)

> > First, should we remove those pins from "ethernet_groups" structure
> > in "drivers/pinctrl/meson/pinctrl-meson8b.c" ?
> I believe that some boards with RMII (100Mbit/s) PHY use TXD0/TXD1 on
> DIF_2_P and DIF_2_N
> so we should keep support for these in the driver
> 
> > Second, following the Odroid-C1+ schematics there are two pins,
> > "eth_rxd2" and "eth_rxd3" which are not configured by the pin controller
> > driver, nor included in the pins group in the relative device tree.
> > Should we configure and include them ?
> interesting - good catch. I think we should include them in both, the
> pinctrl driver and meson8b.dtsi
> do you know which pads are used for "eth_rxd2" and "eth_rxd3"?
>

Following the Odroid-C1+ schematics it seems to me that the differential
pads used for "eth_rxd2" and "eth_rxd3" are exactly DIF_2_P and DIF_2_N.
Infact, comparing the ethernet pads on the schematics and the
"GPIO bank DIF" section on S805 SoC manual, there seems to be
a strict correspondence in the order of the two list of pins.

What do you think ?

> 
> Regards
> Martin

Regards,

Emiliano

[PATCH 0/1] Meson8b RGMII Ethernet pin cleanup

[Martin Blumenstingl]

Hi Emiliano,

On Sun, May 6, 2018 at 11:53 PM, Emiliano Ingrassia
<ingrassia@epigenesys.com> wrote:
> Hi Martin,
>
> On Fri, May 04, 2018 at 10:09:37PM +0200, Martin Blumenstingl wrote:
>> Hi Emiliano,
>>
>> On Thu, May 3, 2018 at 7:06 PM, Emiliano Ingrassia
>> <ingrassia@epigenesys.com> wrote:
>> > Hi Martin,
>> >
>> > the patch seems to work fine but I have two questions.
>> thank you for testing this! :)
>>
>
> Thanks for your patch! :)
>
>> > First, should we remove those pins from "ethernet_groups" structure
>> > in "drivers/pinctrl/meson/pinctrl-meson8b.c" ?
>> I believe that some boards with RMII (100Mbit/s) PHY use TXD0/TXD1 on
>> DIF_2_P and DIF_2_N
>> so we should keep support for these in the driver
>>
>> > Second, following the Odroid-C1+ schematics there are two pins,
>> > "eth_rxd2" and "eth_rxd3" which are not configured by the pin controller
>> > driver, nor included in the pins group in the relative device tree.
>> > Should we configure and include them ?
>> interesting - good catch. I think we should include them in both, the
>> pinctrl driver and meson8b.dtsi
>> do you know which pads are used for "eth_rxd2" and "eth_rxd3"?
>>
>
> Following the Odroid-C1+ schematics it seems to me that the differential
> pads used for "eth_rxd2" and "eth_rxd3" are exactly DIF_2_P and DIF_2_N.
> Infact, comparing the ethernet pads on the schematics and the
> "GPIO bank DIF" section on S805 SoC manual, there seems to be
> a strict correspondence in the order of the two list of pins.
odroid-c1+_rev0.4_20150615.pdf - page 23 almost matches the S805 datasheet:
(left value: Odroid-C1 schematics, right value: S805 datasheet):
- ETH_RXD1 vs ETH_RXD1
- ETH_RXD0 vs ETH_RXD0
- RGMII_RX_CLK vs ETH_RX_DV
- ETH_RX_DV vs ETH_RX_CLK
- ETH_RXD2 vs ETH_TXD0 (questionable in the S805 datasheet?)
- ETH_RXD3 vs ETH_TXD1 (questionable in the S805 datasheet?)
- ETH_PHY_REF_CLK_25MOUT vs ETH_TX_EN
- ETH_TX_EN vs ETH_PHY_REF_CLK
- ETH_MDIO vs ETH_MDC
- ETH_MDC vs ETH_MDIO

> What do you think ?
I think that you made a point here - good catch :)
maybe DIF_2_P and DIF_2_N have different functionality in RMII mode
(TXD0 and TXD1) and RGMII mode (RXD2 and RXD3)?

@Kevin: please ignore this series until we have further clarification
from Amlogic about the function of DIF_2_P and DIF_2_N in RMII/RGMII
mode


Regards
Martin