Re: [PATCH v8 04/11] clk: meson: a1: add support for Amlogic A1 Peripheral clock driver

[Dmitry Rokosov <ddrokosov@sberdevices.ru>]

...

> > +		.ops = &clk_regmap_gate_ro_ops,
> > +		.parent_data = &(const struct clk_parent_data) {
> > +			.fw_name = "xtal",
> > +		},
> > +		.num_parents = 1,
> > +	},
> > +};
> > +
> > +static struct clk_regmap a1_xtal_fixpll = {
> > +	.data = &(struct clk_regmap_gate_data){
> > +		.offset = SYS_OSCIN_CTRL,
> > +		.bit_idx = 1,
> > +	},
> > +	.hw.init = &(struct clk_init_data) {
> > +		.name = "xtal_fixpll",
> 
> same here, this is not a crystal.
> It is the fixpll input gate, what about "fixpll_in"
> 
> Same bellow - you get the idea ...
> 

Yep, got it. Will fix in the v9.

...

> > +static struct clk_regmap a1_rtc_32k_sel = {
> > +	.data = &(struct clk_regmap_mux_data) {
> > +		.offset = RTC_CTRL,
> > +		.mask = 0x3,
> > +		.shift = 0,
> > +		.flags = CLK_MUX_ROUND_CLOSEST,
> > +	},
> > +	.hw.init = &(struct clk_init_data){
> > +		.name = "rtc_32k_sel",
> > +		.ops = &clk_regmap_mux_ops,
> > +		.parent_hws = (const struct clk_hw *[]) {
> > +			&a1_rtc_32k_xtal.hw,
> > +			&a1_rtc_32k_div.hw,
> > +		},
> > +		.num_parents = 2,
> > +		.flags = CLK_SET_RATE_PARENT,
> > +	},
> > +};
> > +
> > +struct clk_regmap a1_rtc_clk = {
> > +	.data = &(struct clk_regmap_gate_data){
> > +		.offset = RTC_BY_OSCIN_CTRL0,
> > +		.bit_idx = 30,
> > +	},
> > +	.hw.init = &(struct clk_init_data){
> > +		.name = "rtc_clk",
> 
> Everytime there is an "_clk" suffix, you can remove it.
> In this driver, we know we are going to get clocks ;)
> 

Exactly! :-)

...

> > +static struct clk_regmap a1_dspa_en = {
> > +	.data = &(struct clk_regmap_gate_data){
> > +		.offset = DSPA_CLK_EN,
> > +		.bit_idx = 1,
> > +	},
> > +	.hw.init = &(struct clk_init_data) {
> > +		.name = "dspa_en",
> > +		.ops = &clk_regmap_gate_ops,
> > +		.parent_hws = (const struct clk_hw *[]) {
> > +			&a1_dspa_sel.hw
> > +		},
> > +		.num_parents = 1,
> > +		.flags = CLK_SET_RATE_PARENT,
> 
> Maybe as a 2nd step, but I suspect a "CLK_SET_RATE_NOREPARENT" is going to
> be needed here at some point.
> 

I will think about it, and try to mark all needed points with that in
the next version.

...

> > +static struct clk_regmap a1_dspb_a = {
> > +	.data = &(struct clk_regmap_gate_data){
> > +		.offset = DSPB_CLK_CTRL0,
> > +		.bit_idx = 13,
> > +	},
> > +	.hw.init = &(struct clk_init_data) {
> > +		.name = "dspb_a",
> > +		.ops = &clk_regmap_gate_ops,
> > +		.parent_hws = (const struct clk_hw *[]) {
> > +			&a1_dspb_a_div.hw
> > +		},
> > +		.num_parents = 1,
> > +		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> 
> Any chance we can remove this CLK_IGNORE_UNUSED, or comment why it is
> needed ?
> 

This is needed for DSP accelerator in the SoC. I'm afraid it can't be
disabled by kernel logic run on Core IP.

...

-- 
Thank you,
Dmitry

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