* [PATCH 0/3] Add T7 PWM core clock support
@ 2026-09-24 15:14 Ronald Claveau via B4 Relay
2026-09-24 15:14 ` [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 Ronald Claveau via B4 Relay
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Ronald Claveau via B4 Relay @ 2026-09-24 15:14 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl
Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel,
linux-amlogic, Ronald Claveau
The PWM controllers on the Amlogic T7 SoC have a system clock that
controls access to the controller, in addition to the two input
clocks of channels A and B.
It is currently not described in the device tree, so it is neither
referenced nor enabled by the driver.
This series adds support for it:
- patch 1 extends the binding with a third "core" clock for
amlogic,t7-pwm, and makes clocks/clock-names required for it;
- patch 2 makes the driver get and enable the optional "core"
clock, leaving other SoCs unaffected;
- patch 3 describes the system clock (CLKID_SYS_PWM_*) in the T7
device tree for all the PWM controllers.
`dt_binding_check DT_SCHEMA_FILES=pwm-amlogic.yaml` test is ok
CHKDT ./Documentation/devicetree/bindings
warning: python package 'yamllint' not installed, skipping
STYLE ./Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/pwm/pwm-amlogic.example.dts
DTC [C] Documentation/devicetree/bindings/pwm/pwm-amlogic.example.dtb
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
---
Ronald Claveau (3):
dt-bindings: pwm: amlogic: Add core clock for T7
pwm: meson: Add optional core clock for S4 PWM
arm64: dts: amlogic: t7: Add core clock to PWM controller nodes
.../devicetree/bindings/pwm/pwm-amlogic.yaml | 37 +++++++++++++++++++---
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 28 ++++++++++++----
drivers/pwm/pwm-meson.c | 5 +++
3 files changed, 59 insertions(+), 11 deletions(-)
---
base-commit: a8c591ed6b672915e0be57843f943a2a723aff40
change-id: 20260924-add-t7-sys-pwm-clk-f0eff81bee21
Best regards,
--
Ronald Claveau <linux-kernel-dev@aliel.fr>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 2026-09-24 15:14 [PATCH 0/3] Add T7 PWM core clock support Ronald Claveau via B4 Relay @ 2026-09-24 15:14 ` Ronald Claveau via B4 Relay 2026-09-24 15:25 ` sashiko-bot 2026-09-24 16:35 ` Conor Dooley 2026-09-24 15:14 ` [PATCH 2/3] pwm: meson: Add optional core clock for S4 PWM Ronald Claveau via B4 Relay 2026-09-24 15:14 ` [PATCH 3/3] arm64: dts: amlogic: t7: Add core clock to PWM controller nodes Ronald Claveau via B4 Relay 2 siblings, 2 replies; 6+ messages in thread From: Ronald Claveau via B4 Relay @ 2026-09-24 15:14 UTC (permalink / raw) To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel, linux-amlogic, Ronald Claveau From: Ronald Claveau <linux-kernel-dev@aliel.fr> The T7 PWM controller has a system clock (the register access clock) in addition to the two input clocks of channels A and B. Add it as a third clock, named "core", for the amlogic,t7-pwm compatible, and require clock-names for this SoC for clarity. The other compatibles are left unchanged. Add an example showing the T7 usage with its fallback to amlogic,meson-s4-pwm. Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr> --- .../devicetree/bindings/pwm/pwm-amlogic.yaml | 37 +++++++++++++++++++--- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml index c337d85da40f1..9212a40d9fe48 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml @@ -62,7 +62,7 @@ properties: clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 power-domains: maxItems: 1 @@ -135,17 +135,38 @@ allOf: properties: compatible: contains: - enum: - - amlogic,meson-s4-pwm + const: amlogic,t7-pwm then: properties: clocks: items: - description: input clock of PWM channel A - description: input clock of PWM channel B - clock-names: false + - description: gate clock for the PWM controller + clock-names: + items: + - const: clk_a + - const: clk_b + - const: core required: - clocks + - clock-names + else: + if: + properties: + compatible: + contains: + enum: + - amlogic,meson-s4-pwm + then: + properties: + clocks: + items: + - description: input clock of PWM channel A + - description: input clock of PWM channel B + clock-names: false + required: + - clocks - if: properties: @@ -182,3 +203,11 @@ examples: clocks = <&pwm_src_a>, <&pwm_src_b>; #pwm-cells = <3>; }; + - | + pwm@60000 { + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; + reg = <0x60000 0x24>; + clocks = <&clk_a>, <&clk_b>, <&core>; + clock-names = "clk_a", "clk_b", "core"; + #pwm-cells = <3>; + }; -- 2.49.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 2026-09-24 15:14 ` [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 Ronald Claveau via B4 Relay @ 2026-09-24 15:25 ` sashiko-bot 2026-09-24 16:35 ` Conor Dooley 1 sibling, 0 replies; 6+ messages in thread From: sashiko-bot @ 2026-09-24 15:25 UTC (permalink / raw) To: Ronald Claveau; +Cc: robh, conor+dt, devicetree, neil.armstrong, linux-amlogic Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] dt-bindings: pwm: amlogic: ABI break for amlogic,t7-pwm -- commit ea055f0ab3ecf76a41b2a2cf99ee615eac00cdc9 Author: Ronald Claveau <linux-kernel-dev@aliel.fr> dt-bindings: pwm: amlogic: Add core clock for T7 This commit adds a third core clock for the amlogic,t7-pwm compatible binding and requires clock-names for this SoC. Other compatibles are left unchanged, and an example is added for T7 usage. > diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml > index c337d85da40f1..9212a40d9fe48 100644 > --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml > +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml [ ... ] > @@ -135,17 +135,38 @@ allOf: > properties: > compatible: > contains: > - enum: > - - amlogic,meson-s4-pwm > + const: amlogic,t7-pwm > then: > properties: > clocks: > items: > - description: input clock of PWM channel A > - description: input clock of PWM channel B > - clock-names: false > + - description: gate clock for the PWM controller > + clock-names: > + items: > + - const: clk_a > + - const: clk_b > + - const: core > required: > - clocks > + - clock-names [Severity: Medium] Does this introduce a schema validation regression for older device trees? By defining exactly three items in the clocks list and strictly requiring the clock-names property, older device trees that only provide two clocks and omit clock-names will fail validation. Device tree schemas typically must maintain backward compatibility with older or out-of-tree DTBs. Should the schema specify a minimum item count of 2 for clocks and only conditionally require clock-names based on the number of clocks provided to avoid an ABI break? -- Sashiko AI review · https://sashiko.dev/#/patchset/20260924-add-t7-sys-pwm-clk-v1-0-05b91e87f0a9@aliel.fr?part=1 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 2026-09-24 15:14 ` [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 Ronald Claveau via B4 Relay 2026-09-24 15:25 ` sashiko-bot @ 2026-09-24 16:35 ` Conor Dooley 1 sibling, 0 replies; 6+ messages in thread From: Conor Dooley @ 2026-09-24 16:35 UTC (permalink / raw) To: linux-kernel-dev Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl, linux-pwm, devicetree, linux-kernel, linux-arm-kernel, linux-amlogic [-- Attachment #1.1: Type: text/plain, Size: 3239 bytes --] On Thu, Sep 24, 2026 at 05:14:28PM +0200, Ronald Claveau via B4 Relay wrote: > From: Ronald Claveau <linux-kernel-dev@aliel.fr> > > The T7 PWM controller has a system clock (the register access clock) > in addition to the two input clocks of channels A and B. Add it as a > third clock, named "core", for the amlogic,t7-pwm compatible, and > require clock-names for this SoC for clarity. What additional clarity does that actually bring? I think it's kinda less clear, because the git history is required to explain why drivers cannot fetch the existing clocks by name. > > The other compatibles are left unchanged. Add an example showing the > T7 usage with its fallback to amlogic,meson-s4-pwm. > > Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr> > --- > .../devicetree/bindings/pwm/pwm-amlogic.yaml | 37 +++++++++++++++++++--- > 1 file changed, 33 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml > index c337d85da40f1..9212a40d9fe48 100644 > --- a/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml > +++ b/Documentation/devicetree/bindings/pwm/pwm-amlogic.yaml > @@ -62,7 +62,7 @@ properties: > > clock-names: > minItems: 1 > - maxItems: 2 > + maxItems: 3 > > power-domains: > maxItems: 1 > @@ -135,17 +135,38 @@ allOf: > properties: > compatible: > contains: > - enum: > - - amlogic,meson-s4-pwm > + const: amlogic,t7-pwm > then: > properties: > clocks: > items: > - description: input clock of PWM channel A > - description: input clock of PWM channel B > - clock-names: false > + - description: gate clock for the PWM controller > + clock-names: > + items: > + - const: clk_a > + - const: clk_b I'd rather "channel-a" or similar, we try not to state the obvious in the names of clocks etc - of course this is a clock! > + - const: core > required: > - clocks > + - clock-names > + else: > + if: > + properties: > + compatible: > + contains: > + enum: > + - amlogic,meson-s4-pwm > + then: > + properties: > + clocks: > + items: > + - description: input clock of PWM channel A > + - description: input clock of PWM channel B > + clock-names: false Are you sure that the s4-pwm doesn't also have this core clock? Seems likely, no? Cheers, Conor. > + required: > + - clocks > > - if: > properties: > @@ -182,3 +203,11 @@ examples: > clocks = <&pwm_src_a>, <&pwm_src_b>; > #pwm-cells = <3>; > }; > + - | > + pwm@60000 { > + compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; > + reg = <0x60000 0x24>; > + clocks = <&clk_a>, <&clk_b>, <&core>; > + clock-names = "clk_a", "clk_b", "core"; > + #pwm-cells = <3>; > + }; > > -- > 2.49.0 > > [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 167 bytes --] _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] pwm: meson: Add optional core clock for S4 PWM 2026-09-24 15:14 [PATCH 0/3] Add T7 PWM core clock support Ronald Claveau via B4 Relay 2026-09-24 15:14 ` [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 Ronald Claveau via B4 Relay @ 2026-09-24 15:14 ` Ronald Claveau via B4 Relay 2026-09-24 15:14 ` [PATCH 3/3] arm64: dts: amlogic: t7: Add core clock to PWM controller nodes Ronald Claveau via B4 Relay 2 siblings, 0 replies; 6+ messages in thread From: Ronald Claveau via B4 Relay @ 2026-09-24 15:14 UTC (permalink / raw) To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel, linux-amlogic, Ronald Claveau From: Ronald Claveau <linux-kernel-dev@aliel.fr> On some SoCs (e.g. T7), the PWM controller has a system clock that must be enabled to access its registers, in addition to the per-channel input clocks. Get and enable it with devm_clk_get_optional_enabled() using the "core" name. The clock is optional, so existing SoCs and device trees that do not provide it keep working unchanged. Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr> --- drivers/pwm/pwm-meson.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 20e6cd07127c4..5ab07322e8d15 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -508,8 +508,13 @@ static int meson_pwm_init_channels_s4(struct pwm_chip *chip) struct device *dev = pwmchip_parent(chip); struct device_node *np = dev->of_node; struct meson_pwm *meson = to_meson_pwm(chip); + struct clk *core_clk; int i, ret; + core_clk = devm_clk_get_optional_enabled(dev, "core"); + if (IS_ERR(core_clk)) + return dev_err_probe(dev, PTR_ERR(core_clk), "Failed to get core clock\n"); + for (i = 0; i < MESON_NUM_PWMS; i++) { meson->channels[i].clk = of_clk_get(np, i); if (IS_ERR(meson->channels[i].clk)) -- 2.49.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] arm64: dts: amlogic: t7: Add core clock to PWM controller nodes 2026-09-24 15:14 [PATCH 0/3] Add T7 PWM core clock support Ronald Claveau via B4 Relay 2026-09-24 15:14 ` [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 Ronald Claveau via B4 Relay 2026-09-24 15:14 ` [PATCH 2/3] pwm: meson: Add optional core clock for S4 PWM Ronald Claveau via B4 Relay @ 2026-09-24 15:14 ` Ronald Claveau via B4 Relay 2 siblings, 0 replies; 6+ messages in thread From: Ronald Claveau via B4 Relay @ 2026-09-24 15:14 UTC (permalink / raw) To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiner Kallweit, Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl Cc: linux-pwm, devicetree, linux-kernel, linux-arm-kernel, linux-amlogic, Ronald Claveau From: Ronald Claveau <linux-kernel-dev@aliel.fr> Describe the system clock of each PWM controller (CLKID_SYS_PWM_*) as a third clock, and add the clock-names property expected by the updated binding: "clk_a", "clk_b" and "core". Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr> --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index 8f3f1c0579a0f..83c597d418875 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -692,7 +692,9 @@ pwm_ao_ef: pwm@30000 { compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg = <0x0 0x30000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_AO_E>, - <&clkc_periphs CLKID_PWM_AO_F>; + <&clkc_periphs CLKID_PWM_AO_F>, + <&clkc_periphs CLKID_SYS_PWM_AO_EF>; + clock-names = "clk_a", "clk_b", "core"; #pwm-cells = <3>; status = "disabled"; }; @@ -701,7 +703,9 @@ pwm_ao_gh: pwm@32000 { compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg = <0x0 0x32000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_AO_G>, - <&clkc_periphs CLKID_PWM_AO_H>; + <&clkc_periphs CLKID_PWM_AO_H>, + <&clkc_periphs CLKID_SYS_PWM_AO_GH>; + clock-names = "clk_a", "clk_b", "core"; #pwm-cells = <3>; status = "disabled"; }; @@ -715,7 +719,9 @@ pwm_ab: pwm@58000 { compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg = <0x0 0x58000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_A>, - <&clkc_periphs CLKID_PWM_B>; + <&clkc_periphs CLKID_PWM_B>, + <&clkc_periphs CLKID_SYS_PWM_AB>; + clock-names = "clk_a", "clk_b", "core"; #pwm-cells = <3>; status = "disabled"; }; @@ -724,7 +730,9 @@ pwm_cd: pwm@5a000 { compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg = <0x0 0x5a000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_C>, - <&clkc_periphs CLKID_PWM_D>; + <&clkc_periphs CLKID_PWM_D>, + <&clkc_periphs CLKID_SYS_PWM_CD>; + clock-names = "clk_a", "clk_b", "core"; #pwm-cells = <3>; status = "disabled"; }; @@ -733,7 +741,9 @@ pwm_ef: pwm@5c000 { compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg = <0x0 0x5c000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_E>, - <&clkc_periphs CLKID_PWM_F>; + <&clkc_periphs CLKID_PWM_F>, + <&clkc_periphs CLKID_SYS_PWM_EF>; + clock-names = "clk_a", "clk_b", "core"; #pwm-cells = <3>; status = "disabled"; }; @@ -742,7 +752,9 @@ pwm_ao_ab: pwm@5e000 { compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg = <0x0 0x5e000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_AO_A>, - <&clkc_periphs CLKID_PWM_AO_B>; + <&clkc_periphs CLKID_PWM_AO_B>, + <&clkc_periphs CLKID_SYS_PWM_AO_AB>; + clock-names = "clk_a", "clk_b", "core"; #pwm-cells = <3>; status = "disabled"; }; @@ -751,7 +763,9 @@ pwm_ao_cd: pwm@60000 { compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg = <0x0 0x60000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_AO_C>, - <&clkc_periphs CLKID_PWM_AO_D>; + <&clkc_periphs CLKID_PWM_AO_D>, + <&clkc_periphs CLKID_SYS_PWM_AO_CD>; + clock-names = "clk_a", "clk_b", "core"; #pwm-cells = <3>; status = "disabled"; }; -- 2.49.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-09-24 16:35 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2026-09-24 15:14 [PATCH 0/3] Add T7 PWM core clock support Ronald Claveau via B4 Relay 2026-09-24 15:14 ` [PATCH 1/3] dt-bindings: pwm: amlogic: Add core clock for T7 Ronald Claveau via B4 Relay 2026-09-24 15:25 ` sashiko-bot 2026-09-24 16:35 ` Conor Dooley 2026-09-24 15:14 ` [PATCH 2/3] pwm: meson: Add optional core clock for S4 PWM Ronald Claveau via B4 Relay 2026-09-24 15:14 ` [PATCH 3/3] arm64: dts: amlogic: t7: Add core clock to PWM controller nodes Ronald Claveau via B4 Relay
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