From: Ronald Claveau via B4 Relay <devnull+linux-kernel-dev.aliel.fr@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Jian Hu <jian.hu@amlogic.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Ronald Claveau <linux-kernel-dev@aliel.fr>
Subject: [PATCH 1/4] clk: meson: g12a: fix fclk_div2p5 multiplier
Date: Thu, 22 Oct 2026 23:52:39 +0200 [thread overview]
Message-ID: <20261022-fix-g12a-clk-v1-1-e2bd8f3f1afa@aliel.fr> (raw)
In-Reply-To: <20261022-fix-g12a-clk-v1-0-e2bd8f3f1afa@aliel.fr>
From: Ronald Claveau <linux-kernel-dev@aliel.fr>
g12a_fclk_div2p5 should be fclk divided by 2.5.
The mult has been declared as 1 which results
as fclk/5 instead of fclk/2.5.
Set mult=2 to get the correct div 2.5 rate.
Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
---
drivers/clk/meson/g12a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index d0d4c7b6dc82..4ec5f15daf98 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -995,7 +995,7 @@ static struct clk_regmap g12a_fclk_div7 = {
};
static struct clk_fixed_factor g12a_fclk_div2p5_div = {
- .mult = 1,
+ .mult = 2,
.div = 5,
.hw.init = &(struct clk_init_data){
.name = "fclk_div2p5_div",
--
2.43.0
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next prev parent reply other threads:[~2026-10-22 21:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-22 21:52 [PATCH 0/4] clk: meson: g12a: fix a few clock definition errors Ronald Claveau via B4 Relay
2026-10-22 21:52 ` Ronald Claveau via B4 Relay [this message]
2026-10-22 22:00 ` [PATCH 1/4] clk: meson: g12a: fix fclk_div2p5 multiplier sashiko-bot
2026-10-22 21:52 ` [PATCH 2/4] clk: meson: g12a: fix swapped VID_PLL and VID_PLL_DIV clock ids Ronald Claveau via B4 Relay
2026-10-22 21:52 ` [PATCH 3/4] clk: meson: g12a: fix swapped VID_PLL and VID_PLL_DIV clock ids for g12b Ronald Claveau via B4 Relay
2026-10-22 21:52 ` [PATCH 4/4] clk: meson: g12a: fix swapped VID_PLL and VID_PLL_DIV clock ids for sm1 Ronald Claveau via B4 Relay
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