* [PATCH v5 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset
2022-12-01 10:30 [PATCH v5 0/7] Support for the NPU in Vim3 Tomeu Vizoso
@ 2022-12-01 10:30 ` Tomeu Vizoso
2022-12-01 12:32 ` Neil Armstrong
2022-12-01 22:22 ` Martin Blumenstingl
2022-12-01 10:30 ` [PATCH v5 2/7] dt-bindings: power: Add G12A NNA power domain Tomeu Vizoso
` (2 subsequent siblings)
3 siblings, 2 replies; 12+ messages in thread
From: Tomeu Vizoso @ 2022-12-01 10:30 UTC (permalink / raw)
Cc: italonicola, Tomeu Vizoso, Neil Armstrong, Philipp Zabel,
Rob Herring, Krzysztof Kozlowski, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
Doesn't appear in the TRM I have, but it is used by the downstream
galcore driver.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
---
include/dt-bindings/reset/amlogic,meson-g12a-reset.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
index 6d487c5eba2c..45f6b8a951d0 100644
--- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
@@ -69,7 +69,9 @@
#define RESET_PARSER_FETCH 72
#define RESET_CTL 73
#define RESET_PARSER_TOP 74
-/* 75-77 */
+/* 75 */
+#define RESET_NNA 76
+/* 77 */
#define RESET_DVALIN 78
#define RESET_HDMITX 79
/* 80-95 */
--
2.38.1
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v5 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset
2022-12-01 10:30 ` [PATCH v5 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
@ 2022-12-01 12:32 ` Neil Armstrong
2022-12-01 22:22 ` Martin Blumenstingl
1 sibling, 0 replies; 12+ messages in thread
From: Neil Armstrong @ 2022-12-01 12:32 UTC (permalink / raw)
To: Tomeu Vizoso
Cc: italonicola, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
On 01/12/2022 11:30, Tomeu Vizoso wrote:
> Doesn't appear in the TRM I have, but it is used by the downstream
> galcore driver.
>
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> include/dt-bindings/reset/amlogic,meson-g12a-reset.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
> index 6d487c5eba2c..45f6b8a951d0 100644
> --- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
> +++ b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h
> @@ -69,7 +69,9 @@
> #define RESET_PARSER_FETCH 72
> #define RESET_CTL 73
> #define RESET_PARSER_TOP 74
> -/* 75-77 */
> +/* 75 */
> +#define RESET_NNA 76
> +/* 77 */
> #define RESET_DVALIN 78
> #define RESET_HDMITX 79
> /* 80-95 */
Missing from https://lore.kernel.org/all/98517f65e600cddf585e53d1ca98cbb7b0b43aee.camel@pengutronix.de/ :
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
No need to send to send a v6 for that, I'll add it while applying after next rc1.
Neil
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset
2022-12-01 10:30 ` [PATCH v5 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
2022-12-01 12:32 ` Neil Armstrong
@ 2022-12-01 22:22 ` Martin Blumenstingl
1 sibling, 0 replies; 12+ messages in thread
From: Martin Blumenstingl @ 2022-12-01 22:22 UTC (permalink / raw)
To: Tomeu Vizoso
Cc: italonicola, Neil Armstrong, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Kevin Hilman, Jerome Brunet,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
On Thu, Dec 1, 2022 at 11:30 AM Tomeu Vizoso <tomeu.vizoso@collabora.com> wrote:
>
> Doesn't appear in the TRM I have, but it is used by the downstream
> galcore driver.
>
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
_______________________________________________
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linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 2/7] dt-bindings: power: Add G12A NNA power domain
2022-12-01 10:30 [PATCH v5 0/7] Support for the NPU in Vim3 Tomeu Vizoso
2022-12-01 10:30 ` [PATCH v5 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
@ 2022-12-01 10:30 ` Tomeu Vizoso
2022-12-01 22:22 ` Martin Blumenstingl
2022-12-01 10:30 ` [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Tomeu Vizoso
2022-12-01 10:30 ` [PATCH v5 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D Tomeu Vizoso
3 siblings, 1 reply; 12+ messages in thread
From: Tomeu Vizoso @ 2022-12-01 10:30 UTC (permalink / raw)
Cc: italonicola, Tomeu Vizoso, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
Add define for the NNA power domain for the NPU in the G12A.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
---
include/dt-bindings/power/meson-g12a-power.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
index bb5e67a842de..93b03bdd60b7 100644
--- a/include/dt-bindings/power/meson-g12a-power.h
+++ b/include/dt-bindings/power/meson-g12a-power.h
@@ -9,5 +9,6 @@
#define PWRC_G12A_VPU_ID 0
#define PWRC_G12A_ETH_ID 1
+#define PWRC_G12A_NNA_ID 2
#endif
--
2.38.1
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 2/7] dt-bindings: power: Add G12A NNA power domain
2022-12-01 10:30 ` [PATCH v5 2/7] dt-bindings: power: Add G12A NNA power domain Tomeu Vizoso
@ 2022-12-01 22:22 ` Martin Blumenstingl
0 siblings, 0 replies; 12+ messages in thread
From: Martin Blumenstingl @ 2022-12-01 22:22 UTC (permalink / raw)
To: Tomeu Vizoso
Cc: italonicola, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Kevin Hilman, Jerome Brunet,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
On Thu, Dec 1, 2022 at 11:30 AM Tomeu Vizoso <tomeu.vizoso@collabora.com> wrote:
>
> Add define for the NNA power domain for the NPU in the G12A.
>
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D
2022-12-01 10:30 [PATCH v5 0/7] Support for the NPU in Vim3 Tomeu Vizoso
2022-12-01 10:30 ` [PATCH v5 1/7] dt-bindings: reset: meson-g12a: Add missing NNA reset Tomeu Vizoso
2022-12-01 10:30 ` [PATCH v5 2/7] dt-bindings: power: Add G12A NNA power domain Tomeu Vizoso
@ 2022-12-01 10:30 ` Tomeu Vizoso
2022-12-01 22:43 ` Martin Blumenstingl
2022-12-01 10:30 ` [PATCH v5 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D Tomeu Vizoso
3 siblings, 1 reply; 12+ messages in thread
From: Tomeu Vizoso @ 2022-12-01 10:30 UTC (permalink / raw)
Cc: italonicola, Tomeu Vizoso, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
Based on power initialization sequence in downstream driver.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
index dd5f2a13ceb5..dfbf0b1c7d29 100644
--- a/drivers/soc/amlogic/meson-ee-pwrc.c
+++ b/drivers/soc/amlogic/meson-ee-pwrc.c
@@ -46,6 +46,9 @@
#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
+#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2)
+#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2)
+
struct meson_ee_pwrc;
struct meson_ee_pwrc_domain;
@@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
+static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \
+ .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \
+ .sleep_mask = BIT(16) | BIT(17), \
+ .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \
+ .iso_mask = BIT(16) | BIT(17), \
+ };
+
/* Memory PD Domains */
#define VPU_MEMPD(__reg) \
@@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
};
+static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
+ { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
+ { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
+};
+
#define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \
{ \
.name = __name, \
@@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
[PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
pwrc_ee_is_powered_off, 11, 2),
[PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
+ [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
+ pwrc_ee_is_powered_off),
};
static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
--
2.38.1
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D
2022-12-01 10:30 ` [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Tomeu Vizoso
@ 2022-12-01 22:43 ` Martin Blumenstingl
2022-12-02 8:53 ` Neil Armstrong
0 siblings, 1 reply; 12+ messages in thread
From: Martin Blumenstingl @ 2022-12-01 22:43 UTC (permalink / raw)
To: Tomeu Vizoso
Cc: italonicola, Neil Armstrong, Kevin Hilman, Jerome Brunet,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
On Thu, Dec 1, 2022 at 11:30 AM Tomeu Vizoso <tomeu.vizoso@collabora.com> wrote:
>
> Based on power initialization sequence in downstream driver.
>
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[...]
> +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
> + { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
> + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
I noticed the discussion in v1 of this series where Neil noted that
you should change GENMASK(31, 0) to GENMASK(23, 0) (for
G12A_HHI_NANOQ_MEM_PD_REG1).
This is all a bit confusing because the S905D3 datasheet mentions that
the HHI_NANOQ_MEM_PD_REG1 register uses the full 32 bits.
I'm still fine with the way it is right now because the datasheets are
not always perfect.
Best regards,
Martin
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D
2022-12-01 22:43 ` Martin Blumenstingl
@ 2022-12-02 8:53 ` Neil Armstrong
0 siblings, 0 replies; 12+ messages in thread
From: Neil Armstrong @ 2022-12-02 8:53 UTC (permalink / raw)
To: Martin Blumenstingl, Tomeu Vizoso
Cc: italonicola, Kevin Hilman, Jerome Brunet,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
On 01/12/2022 23:43, Martin Blumenstingl wrote:
> On Thu, Dec 1, 2022 at 11:30 AM Tomeu Vizoso <tomeu.vizoso@collabora.com> wrote:
>>
>> Based on power initialization sequence in downstream driver.
>>
>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> [...]
>> +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
>> + { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
>> + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
> I noticed the discussion in v1 of this series where Neil noted that
> you should change GENMASK(31, 0) to GENMASK(23, 0) (for
> G12A_HHI_NANOQ_MEM_PD_REG1).
> This is all a bit confusing because the S905D3 datasheet mentions that
> the HHI_NANOQ_MEM_PD_REG1 register uses the full 32 bits.
> I'm still fine with the way it is right now because the datasheets are
> not always perfect.
Yes they're different in G12B & SM1
Neil
>
>
> Best regards,
> Martin
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^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D
2022-12-01 10:30 [PATCH v5 0/7] Support for the NPU in Vim3 Tomeu Vizoso
` (2 preceding siblings ...)
2022-12-01 10:30 ` [PATCH v5 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D Tomeu Vizoso
@ 2022-12-01 10:30 ` Tomeu Vizoso
2022-12-01 22:33 ` Martin Blumenstingl
3 siblings, 1 reply; 12+ messages in thread
From: Tomeu Vizoso @ 2022-12-01 10:30 UTC (permalink / raw)
Cc: italonicola, Tomeu Vizoso, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
This "NPU" is very similar to the Vivante GPUs and Etnaviv works well
with it with just a few small changes.
v2: Add reference to RESET_NNA (Neil)
v3: Fix indentation (Neil)
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 11 +++++++++++
.../boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts | 4 ++++
2 files changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 45947c1031c4..61c8461df614 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/meson-g12a-power.h>
/ {
interrupt-parent = <&gic>;
@@ -2484,4 +2485,14 @@ xtal: xtal-clk {
#clock-cells = <0>;
};
+ npu: npu@ff100000 {
+ compatible = "vivante,gc";
+ reg = <0x0 0xff100000 0x0 0x20000>;
+ interrupts = <0 147 4>;
+ clocks = <&clkc CLKID_NNA_CORE_CLK>,
+ <&clkc CLKID_NNA_AXI_CLK>;
+ clock-names = "core", "bus";
+ resets = <&reset RESET_NNA>;
+ power-domains = <&pwrc PWRC_G12A_NNA_ID>;
+ };
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
index 124a80901084..73f3d87dcefd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dts
@@ -15,6 +15,10 @@ / {
compatible = "khadas,vim3", "amlogic,a311d", "amlogic,g12b";
};
+&npu {
+ status = "okay";
+};
+
/*
* The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
* lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
--
2.38.1
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v5 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D
2022-12-01 10:30 ` [PATCH v5 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D Tomeu Vizoso
@ 2022-12-01 22:33 ` Martin Blumenstingl
2022-12-02 8:57 ` Neil Armstrong
0 siblings, 1 reply; 12+ messages in thread
From: Martin Blumenstingl @ 2022-12-01 22:33 UTC (permalink / raw)
To: Tomeu Vizoso
Cc: italonicola, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Kevin Hilman, Jerome Brunet,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
On Thu, Dec 1, 2022 at 11:31 AM Tomeu Vizoso <tomeu.vizoso@collabora.com> wrote:
[...]
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> index 45947c1031c4..61c8461df614 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
> #include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/power/meson-g12a-power.h>
We could now remove the meson-g12a-power include from
arch/arm64/boot/dts/amlogic/meson-g12.dtsi
I'm not sure if we have any "rule" about this though, so I'm curious
to hear what others think.
Best regards,
Martin
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 4/7] arm64: dts: Add DT node for the VIPNano-QI on the A311D
2022-12-01 22:33 ` Martin Blumenstingl
@ 2022-12-02 8:57 ` Neil Armstrong
0 siblings, 0 replies; 12+ messages in thread
From: Neil Armstrong @ 2022-12-02 8:57 UTC (permalink / raw)
To: Martin Blumenstingl, Tomeu Vizoso
Cc: italonicola, Rob Herring, Krzysztof Kozlowski, Kevin Hilman,
Jerome Brunet,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/Amlogic Meson SoC support,
open list:ARM/Amlogic Meson SoC support, open list
On 01/12/2022 23:33, Martin Blumenstingl wrote:
> On Thu, Dec 1, 2022 at 11:31 AM Tomeu Vizoso <tomeu.vizoso@collabora.com> wrote:
> [...]
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
>> index 45947c1031c4..61c8461df614 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
>> @@ -11,6 +11,7 @@
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
>> #include <dt-bindings/thermal/thermal.h>
>> +#include <dt-bindings/power/meson-g12a-power.h>
> We could now remove the meson-g12a-power include from
> arch/arm64/boot/dts/amlogic/meson-g12.dtsi
> I'm not sure if we have any "rule" about this though, so I'm curious
> to hear what others think.
Actually you're right, Tomeu please remove this include
and remove the:
power-domains = <&pwrc PWRC_G12A_NNA_ID>;
and move it as:
&npu {
power-domains = <&pwrc PWRC_G12A_NNA_ID>;
};
into arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
and while you're at it, please add:
&npu {
power-domains = <&pwrc PWRC_SM1_NNA_ID>;
};
into arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
It's ok to do all this in a single patch.
>
>
> Best regards,
> Martin
(PS: Don't forget Philipp's Acked-by on patch 1 for next version)
Thanks,
Neil
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