[PATCH v2 00/12] soc: amlogic: clk-measure: Add support for more SoCs

[PATCH v2 00/12] soc: amlogic: clk-measure: Add support for more SoCs

[Chuan Liu via B4 Relay]

This patch series adds clk-measure support for the Amlogic A5, A4, S7,
S7D, S6 and A9 SoCs, listed in the order of their release.

The clock names for the clk-measure channels are kept consistent with
those used by the clock driver as much as possible, making it easier to
identify the relationship between the clk-measure channels and the
corresponding clocks in the clock driver.

This patchset also includes an additional patch to optimize memory usage:
  - soc: amlogic: clk-measure: Optimize CLK_MSR_ID to reduce memory usage

To avoid requiring everyone to spend additional effort on a separate
patchset, I have included it in this series. Please feel free to point
out if this is not appropriate for this series.

To improve maintainability, this patchset also includes a patch to reorder
the dt-binding and the compatible entries in the driver.

To minimize unrelated changes, the existing clk-measure channel tables in
the driver are left in their original order. The tables for the newly
supported SoCs are ordered alphabetically.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
Changes in v2:
- Reorder the dt-binding and the compatible entries in the driver
  alphabetically.
- Order the clk-measure channel tables for the newly supported SoCs
  alphabetically.
- Add the const qualifier to the A9 clk-measure channel table.
- Rename "exit_Tsin_B_CLK_IN" to "ext_Tsin_B_CLK_IN" in the A9 clk-measure
  channel table.
- Link to v1: https://lore.kernel.org/r/20260911-more-socs-to-support-clk_measure-v1-0-940e269aa52f@amlogic.com

---
Chuan Liu (12):
      dt-bindings: soc: amlogic: Reordering compatible of clk-measure
      dt-bindings: soc: amlogic: Add clk-measure compatible to support more SoCs
      soc: amlogic: clk-measure: Support more measurement channels
      soc: amlogic: clk-measure: Align compatible entries with DT bindings
      soc: amlogic: clk-measure: Add support for more SoCs
      soc: amlogic: clk-measure: Optimize CLK_MSR_ID to reduce memory usage
      arm64: dts: amlogic: a5: Add clk-measure controller node
      arm64: dts: amlogic: a4: Add clk-measure controller node
      arm64: dts: amlogic: s7: Add clk-measure controller node
      arm64: dts: amlogic: s7d: Add clk-measure controller node
      arm64: dts: amlogic: s6: Add clk-measure controller node
      arm64: dts: amlogic: a9: Add clk-measure controller node

 .../soc/amlogic/amlogic,meson-gx-clk-measure.yaml  |  16 +-
 arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi        |   5 +
 arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi        |   5 +
 arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi        |   5 +
 arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi        |   5 +
 arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi        |   5 +
 arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi       |   5 +
 drivers/soc/amlogic/meson-clk-measure.c            | 927 ++++++++++++++++++++-
 8 files changed, 953 insertions(+), 20 deletions(-)
---
base-commit: a2530c83c458a503e55219966217dfd1c36a385e
change-id: 20260710-more-socs-to-support-clk_measure-c826f8ab9e68

Best regards,
-- 
Chuan Liu <chuan.liu@amlogic.com>



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[PATCH v2 01/12] dt-bindings: soc: amlogic: Reordering compatible of clk-measure

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Sort the compatible properties defined by clk-measure in alphabetical
order.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 .../bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml     | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml
index b1200e6940ac..ad37eca48103 100644
--- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml
+++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml
@@ -16,15 +16,15 @@ maintainers:
 properties:
   compatible:
     enum:
-      - amlogic,meson-gx-clk-measure
-      - amlogic,meson8-clk-measure
-      - amlogic,meson8b-clk-measure
+      - amlogic,a1-clk-measure
+      - amlogic,c3-clk-measure
       - amlogic,meson-axg-clk-measure
       - amlogic,meson-g12a-clk-measure
+      - amlogic,meson-gx-clk-measure
       - amlogic,meson-sm1-clk-measure
-      - amlogic,c3-clk-measure
+      - amlogic,meson8-clk-measure
+      - amlogic,meson8b-clk-measure
       - amlogic,s4-clk-measure
-      - amlogic,a1-clk-measure
       - amlogic,t7-clk-measure
 
   reg:

-- 
2.42.0



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Re: [PATCH v2 01/12] dt-bindings: soc: amlogic: Reordering compatible of clk-measure

[Krzysztof Kozlowski]

On Sun, Sep 20, 2026 at 06:25:03PM +0800, Chuan Liu wrote:
> Sort the compatible properties defined by clk-measure in alphabetical
> order.
> 
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
>  .../bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml     | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof


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[PATCH v2 02/12] dt-bindings: soc: amlogic: Add clk-measure compatible to support more SoCs

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Add clk-measure compatible for amlogic A5, A4, S7, S7D, S6 and A9 SoCs.

Although the clk-measure IP itself has little hardware difference across
SoCs, the clock inputs connected to the clk-measure block vary between
SoCs. Therefore, it is difficult to fall back to the configuration used
by previous SoCs.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 .../bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml          | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml
index ad37eca48103..16893f427532 100644
--- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml
+++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml
@@ -17,6 +17,9 @@ properties:
   compatible:
     enum:
       - amlogic,a1-clk-measure
+      - amlogic,a4-clk-measure
+      - amlogic,a5-clk-measure
+      - amlogic,a9-clk-measure
       - amlogic,c3-clk-measure
       - amlogic,meson-axg-clk-measure
       - amlogic,meson-g12a-clk-measure
@@ -25,6 +28,9 @@ properties:
       - amlogic,meson8-clk-measure
       - amlogic,meson8b-clk-measure
       - amlogic,s4-clk-measure
+      - amlogic,s6-clk-measure
+      - amlogic,s7-clk-measure
+      - amlogic,s7d-clk-measure
       - amlogic,t7-clk-measure
 
   reg:

-- 
2.42.0



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Re: [PATCH v2 02/12] dt-bindings: soc: amlogic: Add clk-measure compatible to support more SoCs

[Krzysztof Kozlowski]

On Sun, Sep 20, 2026 at 06:25:04PM +0800, Chuan Liu wrote:
> Add clk-measure compatible for amlogic A5, A4, S7, S7D, S6 and A9 SoCs.
> 
> Although the clk-measure IP itself has little hardware difference across
> SoCs, the clock inputs connected to the clk-measure block vary between
> SoCs. Therefore, it is difficult to fall back to the configuration used
> by previous SoCs.
> 
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
>  .../bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml          | 6 ++++++
>  1 file changed, 6 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof


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[PATCH v2 03/12] soc: amlogic: clk-measure: Support more measurement channels

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

On S4 and C3, as well as later SoCs, the clk-measure IP expands the
number of supported measurement channels from 128 to 256. Accordingly,
the MSR_CLK_SRC field in the register is extended from 7 bits to 8 bits.

To support both the old and new implementations, the driver now
uniformly defines the valid MSR_CLK_SRC field as bits[27:20].

For SoCs where MSR_CLK_SRC is only 7 bits wide, the driver never sets
bit27, and on those SoCs bit27 is read-only. Therefore, using
bits[27:20] as the unified field definition does not introduce any
behavioral change or compatibility issue for existing SoCs.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 drivers/soc/amlogic/meson-clk-measure.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c
index 8a1a9fed0e74..0d4ba2555d17 100644
--- a/drivers/soc/amlogic/meson-clk-measure.c
+++ b/drivers/soc/amlogic/meson-clk-measure.c
@@ -20,7 +20,7 @@ static DEFINE_MUTEX(measure_lock);
 #define MSR_CONT		BIT(17) /* continuous measurement */
 #define MSR_INTR		BIT(18) /* interrupts */
 #define MSR_RUN			BIT(19)
-#define MSR_CLK_SRC		GENMASK(26, 20)
+#define MSR_CLK_SRC		GENMASK(27, 20)
 #define MSR_BUSY		BIT(31)
 
 #define MSR_VAL_MASK		GENMASK(15, 0)

-- 
2.42.0



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[PATCH v2 04/12] soc: amlogic: clk-measure: Align compatible entries with DT bindings

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Reorder the meson_msr_match_table entries to match the order of the
compatible strings in the DT binding.

Move the newly added clk_msr_a1_data entry accordingly, while keeping
the existing SoC-specific data order unchanged.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 drivers/soc/amlogic/meson-clk-measure.c | 40 ++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c
index 0d4ba2555d17..d58c8d9629ea 100644
--- a/drivers/soc/amlogic/meson-clk-measure.c
+++ b/drivers/soc/amlogic/meson-clk-measure.c
@@ -1279,6 +1279,12 @@ static const struct msr_reg_offset msr_reg_offset_v2 = {
 	.duty_val = 0x18,
 };
 
+static const struct meson_msr_data clk_msr_a1_data = {
+	.msr_table = (void *)clk_msr_a1,
+	.msr_count = ARRAY_SIZE(clk_msr_a1),
+	.reg = &msr_reg_offset_v2,
+};
+
 static const struct meson_msr_data clk_msr_c3_data = {
 	.msr_table = (void *)clk_msr_c3,
 	.msr_count = ARRAY_SIZE(clk_msr_c3),
@@ -1291,12 +1297,6 @@ static const struct meson_msr_data clk_msr_s4_data = {
 	.reg = &msr_reg_offset_v2,
 };
 
-static const struct meson_msr_data clk_msr_a1_data = {
-	.msr_table = (void *)clk_msr_a1,
-	.msr_count = ARRAY_SIZE(clk_msr_a1),
-	.reg = &msr_reg_offset_v2,
-};
-
 static const struct meson_msr_data clk_msr_t7_data = {
 	.msr_table = (void *)clk_msr_t7,
 	.msr_count = ARRAY_SIZE(clk_msr_t7),
@@ -1305,16 +1305,12 @@ static const struct meson_msr_data clk_msr_t7_data = {
 
 static const struct of_device_id meson_msr_match_table[] = {
 	{
-		.compatible = "amlogic,meson-gx-clk-measure",
-		.data = &clk_msr_gx_data,
-	},
-	{
-		.compatible = "amlogic,meson8-clk-measure",
-		.data = &clk_msr_m8_data,
+		.compatible = "amlogic,a1-clk-measure",
+		.data = &clk_msr_a1_data,
 	},
 	{
-		.compatible = "amlogic,meson8b-clk-measure",
-		.data = &clk_msr_m8_data,
+		.compatible = "amlogic,c3-clk-measure",
+		.data = &clk_msr_c3_data,
 	},
 	{
 		.compatible = "amlogic,meson-axg-clk-measure",
@@ -1324,21 +1320,25 @@ static const struct of_device_id meson_msr_match_table[] = {
 		.compatible = "amlogic,meson-g12a-clk-measure",
 		.data = &clk_msr_g12a_data,
 	},
+	{
+		.compatible = "amlogic,meson-gx-clk-measure",
+		.data = &clk_msr_gx_data,
+	},
 	{
 		.compatible = "amlogic,meson-sm1-clk-measure",
 		.data = &clk_msr_sm1_data,
 	},
 	{
-		.compatible = "amlogic,c3-clk-measure",
-		.data = &clk_msr_c3_data,
+		.compatible = "amlogic,meson8-clk-measure",
+		.data = &clk_msr_m8_data,
 	},
 	{
-		.compatible = "amlogic,s4-clk-measure",
-		.data = &clk_msr_s4_data,
+		.compatible = "amlogic,meson8b-clk-measure",
+		.data = &clk_msr_m8_data,
 	},
 	{
-		.compatible = "amlogic,a1-clk-measure",
-		.data = &clk_msr_a1_data,
+		.compatible = "amlogic,s4-clk-measure",
+		.data = &clk_msr_s4_data,
 	},
 	{
 		.compatible = "amlogic,t7-clk-measure",

-- 
2.42.0



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[PATCH v2 05/12] soc: amlogic: clk-measure: Add support for more SoCs

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Add clk-measure driver support for Amlogic A5, A4, S7, S7D, S6 and A9
SoCs.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 drivers/soc/amlogic/meson-clk-measure.c | 897 ++++++++++++++++++++++++++++++++
 1 file changed, 897 insertions(+)

diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c
index d58c8d9629ea..50928ac14f86 100644
--- a/drivers/soc/amlogic/meson-clk-measure.c
+++ b/drivers/soc/amlogic/meson-clk-measure.c
@@ -1041,6 +1041,843 @@ static const struct meson_msr_id clk_msr_t7[] = {
 	CLK_MSR_ID(222, "enc0")
 };
 
+static const struct meson_msr_id clk_msr_a4[] = {
+	CLK_MSR_ID(0, "sys_clk"),
+	CLK_MSR_ID(1, "axi_clk"),
+	CLK_MSR_ID(2, "rtc_clk"),
+	CLK_MSR_ID(3, "p22_usb2_ckout"),
+	CLK_MSR_ID(4, "p21_usb2_ckout"),
+	CLK_MSR_ID(5, "p20_usb2_ckout"),
+	CLK_MSR_ID(6, "cpu_clk_div16"),
+	CLK_MSR_ID(8, "eth_mpll_test"),
+	CLK_MSR_ID(10, "fclk_div5"),
+	CLK_MSR_ID(15, "fclk_50m"),
+	CLK_MSR_ID(16, "sys_oscin32k_i"),
+	CLK_MSR_ID(17, "rtc_pll"),
+	CLK_MSR_ID(19, "hifi_pll"),
+	CLK_MSR_ID(20, "gp0_pll"),
+	CLK_MSR_ID(21, "gp1_pll"),
+	CLK_MSR_ID(22, "eth_mppll_50m_ckout"),
+	CLK_MSR_ID(23, "sys_pll_div16"),
+	CLK_MSR_ID(24, "ddr_dpll_pt_clk"),
+	CLK_MSR_ID(27, "rtc_sec_pulse_out"),
+	CLK_MSR_ID(28, "rtc_osc_clk_out"),
+	CLK_MSR_ID(30, "mod_eth_phy_ref_clk"),
+	CLK_MSR_ID(31, "mod_eth_tx_clk"),
+	CLK_MSR_ID(32, "eth_125m"),
+	CLK_MSR_ID(33, "eth_rmii"),
+	CLK_MSR_ID(34, "co_clkin_to_mac"),
+	CLK_MSR_ID(35, "mod_eth_rx_clk_rmii"),
+	CLK_MSR_ID(36, "co_rx_clk"),
+	CLK_MSR_ID(37, "co_tx_clk"),
+	CLK_MSR_ID(38, "eth_phy_rxclk"),
+	CLK_MSR_ID(39, "eth_phy_plltxclk"),
+	CLK_MSR_ID(40, "ephy_test_clk"),
+	CLK_MSR_ID(41, "audio_core"),
+	CLK_MSR_ID(51, "cts_vout_venc_clk_ph"),
+	CLK_MSR_ID(52, "cts_vout_venc_clk"),
+	CLK_MSR_ID(106, "deskew_pll_test_clk"),
+	CLK_MSR_ID(111, "sar_adc"),
+	CLK_MSR_ID(112, "ts"),
+	CLK_MSR_ID(113, "sd_emmc_c"),
+	CLK_MSR_ID(115, "sd_emmc_a"),
+	CLK_MSR_ID(116, "gpio_msr_clk"),
+	CLK_MSR_ID(117, "spicc1"),
+	CLK_MSR_ID(118, "spicc0"),
+	CLK_MSR_ID(119, "o_mst_sclk_vad"),
+	CLK_MSR_ID(120, "o_mst_mclk_vad"),
+	CLK_MSR_ID(121, "o_pdm_sysclk"),
+	CLK_MSR_ID(122, "mod_audio_pdm_dclk_o"),
+	CLK_MSR_ID(123, "o_vad_clk"),
+	CLK_MSR_ID(124, "earcrx_dmac_clk"),
+	CLK_MSR_ID(125, "earcrx_cmdc_clk"),
+	CLK_MSR_ID(126, "earctx_dmac_clk"),
+	CLK_MSR_ID(127, "earctx_cmdc_clk"),
+	CLK_MSR_ID(128, "tohdmitx_bclk"),
+	CLK_MSR_ID(129, "tohdmitx_mclk"),
+	CLK_MSR_ID(130, "tohdmitx_spdif_clk"),
+	CLK_MSR_ID(131, "toacodec_bclk"),
+	CLK_MSR_ID(132, "toacodec_mclk"),
+	CLK_MSR_ID(133, "spdifout_b_mst_clk"),
+	CLK_MSR_ID(134, "spdifout_mst_clk"),
+	CLK_MSR_ID(135, "spdifin_mst_clk"),
+	CLK_MSR_ID(136, "audio_mclk"),
+	CLK_MSR_ID(137, "vad_clk"),
+	CLK_MSR_ID(138, "tdmout_d_sclk"),
+	CLK_MSR_ID(139, "tdmout_c_sclk"),
+	CLK_MSR_ID(140, "tdmout_b_sclk"),
+	CLK_MSR_ID(141, "tdmout_a_sclk"),
+	CLK_MSR_ID(142, "tdminb_lb_sclk"),
+	CLK_MSR_ID(143, "tdmin_lb_sclk"),
+	CLK_MSR_ID(144, "tdmin_d_sclk"),
+	CLK_MSR_ID(145, "tdmin_c_sclk"),
+	CLK_MSR_ID(146, "tdmin_b_sclk"),
+	CLK_MSR_ID(147, "tdmin_a_sclk"),
+	CLK_MSR_ID(148, "resampleb_clk"),
+	CLK_MSR_ID(149, "resamplea_clk"),
+	CLK_MSR_ID(150, "pdmb_sysclk"),
+	CLK_MSR_ID(151, "pdmb_dclk"),
+	CLK_MSR_ID(152, "pdm_sysclk"),
+	CLK_MSR_ID(153, "pdm_dclk"),
+	CLK_MSR_ID(154, "alockerb_out_clk"),
+	CLK_MSR_ID(155, "alockerb_in_clk"),
+	CLK_MSR_ID(156, "alocker_out_clk"),
+	CLK_MSR_ID(157, "alocker_in_clk"),
+	CLK_MSR_ID(158, "audio_mst_clk[34]"),
+	CLK_MSR_ID(159, "audio_mst_clk[35]"),
+	CLK_MSR_ID(162, "pwm_h"),
+	CLK_MSR_ID(163, "pwm_g"),
+	CLK_MSR_ID(164, "pwm_f"),
+	CLK_MSR_ID(165, "pwm_e"),
+	CLK_MSR_ID(166, "pwm_d"),
+	CLK_MSR_ID(167, "pwm_c"),
+	CLK_MSR_ID(168, "pwm_b"),
+	CLK_MSR_ID(169, "pwm_a"),
+	CLK_MSR_ID(170, "AU_ADC_CLK_G128X"),
+	CLK_MSR_ID(171, "AU_ADC_CLK_TO_GPIO"),
+	CLK_MSR_ID(172, "AU_DAC1_CLK_G128X"),
+	CLK_MSR_ID(173, "AU_DAC1_CLK_TO_GPIO"),
+	CLK_MSR_ID(176, "rng_ring_osc_clk[0]"),
+	CLK_MSR_ID(177, "rng_ring_osc_clk[1]"),
+	CLK_MSR_ID(178, "rng_ring_osc_clk[2]"),
+	CLK_MSR_ID(179, "rng_ring_osc_clk[3]"),
+	CLK_MSR_ID(180, "sys_cpu_osc_ring[0](ULVT16)"),
+	CLK_MSR_ID(181, "sys_cpu_osc_ring[1](ULVT20)"),
+	CLK_MSR_ID(182, "sys_cpu_osc_ring[2](ULVT16)"),
+	CLK_MSR_ID(183, "sys_cpu_osc_ring[3](ULVT16)"),
+	CLK_MSR_ID(184, "sys_cpu_osc_ring[4](ULVT16)"),
+	CLK_MSR_ID(185, "am_ring_osc_clk_out_top[0](SVT16)"),
+	CLK_MSR_ID(186, "am_ring_osc_clk_out_top[1](LVT20)"),
+};
+
+static const struct meson_msr_id clk_msr_a5[] = {
+	CLK_MSR_ID(0, "sys_clk"),
+	CLK_MSR_ID(1, "axi_clk"),
+	CLK_MSR_ID(2, "rtc_clk"),
+	CLK_MSR_ID(3, "dspa"),
+	CLK_MSR_ID(6, "cpu_clk_div16"),
+	CLK_MSR_ID(10, "fclk_div5"),
+	CLK_MSR_ID(11, "mpll0"),
+	CLK_MSR_ID(12, "mpll1"),
+	CLK_MSR_ID(13, "mpll2"),
+	CLK_MSR_ID(14, "mpll3"),
+	CLK_MSR_ID(15, "fclk_50m"),
+	CLK_MSR_ID(16, "sys_oscin32k_i"),
+	CLK_MSR_ID(17, "rtc_pll"),
+	CLK_MSR_ID(18, "mpll_clk_test_out"),
+	CLK_MSR_ID(19, "hifi_pll"),
+	CLK_MSR_ID(20, "gp0_pll"),
+	CLK_MSR_ID(21, "gp1_pll"),
+	CLK_MSR_ID(23, "sys_pll_div16"),
+	CLK_MSR_ID(24, "ddr_dpll_pt_clk"),
+	CLK_MSR_ID(25, "nna_axi"),
+	CLK_MSR_ID(26, "nna_core"),
+	CLK_MSR_ID(27, "rtc_sec_pulse_out"),
+	CLK_MSR_ID(28, "rtc_osc_clk_out"),
+	CLK_MSR_ID(30, "mod_eth_phy_ref_clk"),
+	CLK_MSR_ID(31, "mod_eth_tx_clk"),
+	CLK_MSR_ID(35, "mod_eth_rx_clk_rmii"),
+	CLK_MSR_ID(79, "rama_clk"),
+	CLK_MSR_ID(106, "deskew_pll_clk_div32_out"),
+	CLK_MSR_ID(111, "sar_adc"),
+	CLK_MSR_ID(112, "ts"),
+	CLK_MSR_ID(113, "sd_emmc_c"),
+	CLK_MSR_ID(115, "sd_emmc_a"),
+	CLK_MSR_ID(116, "gpio_msr_clk"),
+	CLK_MSR_ID(117, "spicc1"),
+	CLK_MSR_ID(118, "spicc0"),
+	CLK_MSR_ID(119, "o_mst_sclk_vad"),
+	CLK_MSR_ID(120, "o_mst_mclk_vad"),
+	CLK_MSR_ID(121, "o_pdm_sysclk"),
+	CLK_MSR_ID(122, "mod_audio_pdm_dclk_o"),
+	CLK_MSR_ID(123, "o_vad_clk"),
+	CLK_MSR_ID(124, "earcrx_dmac_clk"),
+	CLK_MSR_ID(125, "earcrx_cmdc_clk"),
+	CLK_MSR_ID(126, "earctx_dmac_clk"),
+	CLK_MSR_ID(127, "earctx_cmdc_clk"),
+	CLK_MSR_ID(128, "tohdmitx_bclk"),
+	CLK_MSR_ID(129, "tohdmitx_mclk"),
+	CLK_MSR_ID(130, "tohdmitx_spdif_clk"),
+	CLK_MSR_ID(131, "toacodec_bclk"),
+	CLK_MSR_ID(132, "toacodec_mclk"),
+	CLK_MSR_ID(133, "spdifout_b_mst_clk"),
+	CLK_MSR_ID(134, "spdifout_mst_clk"),
+	CLK_MSR_ID(135, "spdifin_mst_clk"),
+	CLK_MSR_ID(136, "audio_mclk"),
+	CLK_MSR_ID(137, "vad_clk"),
+	CLK_MSR_ID(138, "tdmout_d_sclk"),
+	CLK_MSR_ID(139, "tdmout_c_sclk"),
+	CLK_MSR_ID(140, "tdmout_b_sclk"),
+	CLK_MSR_ID(141, "tdmout_a_sclk"),
+	CLK_MSR_ID(142, "tdminb_lb_sclk"),
+	CLK_MSR_ID(143, "tdmin_lb_sclk"),
+	CLK_MSR_ID(144, "tdmin_d_sclk"),
+	CLK_MSR_ID(145, "tdmin_c_sclk"),
+	CLK_MSR_ID(146, "tdmin_b_sclk"),
+	CLK_MSR_ID(147, "tdmin_a_sclk"),
+	CLK_MSR_ID(148, "resampleb_clk"),
+	CLK_MSR_ID(149, "resamplea_clk"),
+	CLK_MSR_ID(150, "pdmb_sysclk"),
+	CLK_MSR_ID(151, "pdmb_dclk"),
+	CLK_MSR_ID(152, "pdm_sysclk"),
+	CLK_MSR_ID(153, "pdm_dclk"),
+	CLK_MSR_ID(154, "alockerb_out_clk"),
+	CLK_MSR_ID(155, "alockerb_in_clk"),
+	CLK_MSR_ID(156, "alocker_out_clk"),
+	CLK_MSR_ID(157, "alocker_in_clk"),
+	CLK_MSR_ID(158, "audio_mst_clk[34]"),
+	CLK_MSR_ID(159, "audio_mst_clk[35]"),
+	CLK_MSR_ID(162, "pwm_h"),
+	CLK_MSR_ID(163, "pwm_g"),
+	CLK_MSR_ID(164, "pwm_f"),
+	CLK_MSR_ID(165, "pwm_e"),
+	CLK_MSR_ID(166, "pwm_d"),
+	CLK_MSR_ID(167, "pwm_c"),
+	CLK_MSR_ID(168, "pwm_b"),
+	CLK_MSR_ID(169, "pwm_a"),
+	CLK_MSR_ID(176, "rng_ring_osc_clk[0]"),
+	CLK_MSR_ID(177, "rng_ring_osc_clk[1]"),
+	CLK_MSR_ID(178, "rng_ring_osc_clk[2]"),
+	CLK_MSR_ID(179, "rng_ring_osc_clk[3]"),
+	CLK_MSR_ID(180, "dmc_osc_ring(LVT16)"),
+	CLK_MSR_ID(181, "dsp_osc_ring(SVT16)"),
+	CLK_MSR_ID(182, "axi_srama_osc_ring(SVT16)"),
+	CLK_MSR_ID(183, "nna_osc_ring[0](ULVT20)"),
+	CLK_MSR_ID(184, "nna_osc_ring[1](LVT16)"),
+	CLK_MSR_ID(185, "sys_cpu_osc_ring[0](ULVT16)"),
+	CLK_MSR_ID(186, "sys_cpu_osc_ring[1](ULVT20)"),
+	CLK_MSR_ID(187, "sys_cpu_osc_ring[2](ULVT16)"),
+	CLK_MSR_ID(188, "sys_cpu_osc_ring[3](LVT16)"),
+	CLK_MSR_ID(189, "axi_sramb_osc_ring(SVT16)"),
+};
+
+static const struct meson_msr_id clk_msr_a9[] = {
+	CLK_MSR_ID(0,  "sys_clk"),
+	CLK_MSR_ID(1,  "axi_clk"),
+	CLK_MSR_ID(2,  "rtc_clk"),
+	CLK_MSR_ID(3,  "dspa"),
+	CLK_MSR_ID(4,  "mali_stack"),
+	CLK_MSR_ID(5,  "mali"),
+	CLK_MSR_ID(6,  "cpu_clk_div16"),
+	CLK_MSR_ID(7,  "a78_clk_div16"),
+	CLK_MSR_ID(8,  "dsu_clk_div16"),
+	CLK_MSR_ID(9,  "isp"),
+	CLK_MSR_ID(10, "gp2_pll"),
+	CLK_MSR_ID(11, "fclk_div5"),
+	CLK_MSR_ID(12, "u2drd_usb2_ckout"),
+	CLK_MSR_ID(13, "pre0_hdmirx_aud_pll_clk"),
+	CLK_MSR_ID(14, "hrx20_pll_clk_test"),
+	CLK_MSR_ID(15, "u2h_usb2_ckout"),
+	CLK_MSR_ID(16, "fclk_50m"),
+	CLK_MSR_ID(17, "u3drd_b_usb2_ckout"),
+	CLK_MSR_ID(18, "gp1_pll"),
+	CLK_MSR_ID(19, "hifi_pll"),
+	CLK_MSR_ID(20, "gp0_pll"),
+	CLK_MSR_ID(21, "hifi1_pll"),
+	CLK_MSR_ID(22, "csi_phy"),
+	CLK_MSR_ID(23, "sys_pll_div16"),
+	CLK_MSR_ID(24, "ddr_dpll_pt_clk"),
+	CLK_MSR_ID(25, "mod_Tsin_A_CLK_IN"),
+	CLK_MSR_ID(26, "ext_Tsin_B_CLK_IN"),
+	CLK_MSR_ID(27, "u3p2pll1_0_clk_div16"),
+	CLK_MSR_ID(28, "u3p2pll1_1_clk_div16"),
+	CLK_MSR_ID(29, "upcrx0_cdrclk"),
+	CLK_MSR_ID(30, "upcrx1_cdrclk"),
+	CLK_MSR_ID(31, "hdmirx_aud_sck"),
+	CLK_MSR_ID(32, "uptx0_clk_sync_b20"),
+	CLK_MSR_ID(33, "uptx1_clk_sync_b20"),
+	CLK_MSR_ID(34, "lp_pll_clk0"),
+	CLK_MSR_ID(35, "lp_pll_clk1"),
+	CLK_MSR_ID(36, "u3hsg_PCIE_PIPE_PCLK"),
+	CLK_MSR_ID(37, "u3hsg_upcrx_cdrclk"),
+	CLK_MSR_ID(38, "u3hsg_upctx_clk_sync_b20"),
+	CLK_MSR_ID(39, "u3hsg_upcrxpll_clk_test"),
+	CLK_MSR_ID(40, "hdmirx_acr_lclk"),
+	CLK_MSR_ID(41, "i3c"),
+	CLK_MSR_ID(42, "hdmirx_aud_pll"),
+	CLK_MSR_ID(43, "hdmirx_acr_ref"),
+	CLK_MSR_ID(44, "hdmirx_meter"),
+	CLK_MSR_ID(45, "hdmirx_hdcp2x"),
+	CLK_MSR_ID(46, "hdmirx_5m"),
+	CLK_MSR_ID(47, "hdmirx_2m"),
+	CLK_MSR_ID(48, "hdmirx_cfg"),
+	CLK_MSR_ID(49, "hdmi_vx1_pix_clk"),
+	CLK_MSR_ID(50, "vid_pll"),
+	CLK_MSR_ID(51, "encoder0_if_clk"),
+	CLK_MSR_ID(52, "encoder1"),
+	CLK_MSR_ID(53, "encoder0"),
+	CLK_MSR_ID(54, "vdac"),
+	CLK_MSR_ID(55, "mali_aclkm"),
+	CLK_MSR_ID(56, "vid1_pll"),
+	CLK_MSR_ID(57, "lcd_an_ph2"),
+	CLK_MSR_ID(58, "lcd_an_ph3"),
+	CLK_MSR_ID(59, "hdmitx_pixel"),
+	CLK_MSR_ID(60, "vdin_meas"),
+	CLK_MSR_ID(61, "vpu"),
+	CLK_MSR_ID(62, "vpu_clkb"),
+	CLK_MSR_ID(63, "vpu_clkb_tmp"),
+	CLK_MSR_ID(64, "u3p2_upcrxpll_fst_pll_clk"),
+	CLK_MSR_ID(65, "vid_lock"),
+	CLK_MSR_ID(66, "vapb"),
+	CLK_MSR_ID(67, "ge2d"),
+	CLK_MSR_ID(68, "cve"),
+	CLK_MSR_ID(69, "vge"),
+	CLK_MSR_ID(70, "dsi0_meas"),
+	CLK_MSR_ID(71, "dsi1_meas"),
+	CLK_MSR_ID(72, "mipi_csi_phy_clk_out[0]"),
+	CLK_MSR_ID(73, "mipi_csi_phy_clk_out[1]"),
+	CLK_MSR_ID(74, "mipi_csi_phy_clk_out[2]"),
+	CLK_MSR_ID(75, "mipi_csi_phy_clk_out[3]"),
+	CLK_MSR_ID(76, "hdmitx_tmds"),
+	CLK_MSR_ID(77, "hdmitx_sys"),
+	CLK_MSR_ID(78, "hdmitx_fe"),
+	CLK_MSR_ID(80, "hdmitx_prif"),
+	CLK_MSR_ID(81, "hdmitx_200m"),
+	CLK_MSR_ID(82, "hdmitx_aud"),
+	CLK_MSR_ID(83, "hdmitx1_pixel"),
+	CLK_MSR_ID(84, "hdmitx1_fe"),
+	CLK_MSR_ID(85, "gic"),
+	CLK_MSR_ID(86, "lvds0_fifo_clk"),
+	CLK_MSR_ID(87, "lvds1_fifo_clk"),
+	CLK_MSR_ID(88, "htx_aes_clk"),
+	CLK_MSR_ID(89, "amfc"),
+	CLK_MSR_ID(90, "a_clk_sync_dig"),
+	CLK_MSR_ID(91, "b_clk_sync_dig"),
+	CLK_MSR_ID(92, "u3dp_upcrx_cdrclk"),
+	CLK_MSR_ID(93, "u3dp_upctx_clk_sync_b20"),
+	CLK_MSR_ID(94, "u3dp_upcrxpll_clk_test"),
+	CLK_MSR_ID(95, "u3dp_upcrpll_fst_pll_clk"),
+	CLK_MSR_ID(96, "u3dp_usb2_ckout"),
+	CLK_MSR_ID(97, "hcodec"),
+	CLK_MSR_ID(99, "hevcf"),
+	CLK_MSR_ID(104, "spisg2"),
+	CLK_MSR_ID(105, "spisg1"),
+	CLK_MSR_ID(106, "deskew_pll_clk_div32_out"),
+	CLK_MSR_ID(108, "cmpr"),
+	CLK_MSR_ID(109, "dewarpa"),
+	CLK_MSR_ID(110, "sc"),
+	CLK_MSR_ID(111, "sar_adc"),
+	CLK_MSR_ID(112, "glb"),
+	CLK_MSR_ID(113, "sd_emmc_c"),
+	CLK_MSR_ID(114, "sd_emmc_b"),
+	CLK_MSR_ID(115, "sd_emmc_a"),
+	CLK_MSR_ID(116, "gpio_msr_clk"),
+	CLK_MSR_ID(117, "aux_clk_o"),
+	CLK_MSR_ID(118, "spisg0"),
+	CLK_MSR_ID(121, "ts"),
+	CLK_MSR_ID(122, "usb_48m"),
+	CLK_MSR_ID(123, "usb_250m"),
+	CLK_MSR_ID(124, "eth_125m"),
+	CLK_MSR_ID(125, "eth_rmii"),
+	CLK_MSR_ID(126, "hrx20_tmds20_clk"),
+	CLK_MSR_ID(127, "hrx20_cable_clk"),
+	CLK_MSR_ID(128, "hdmirx_vid_clk"),
+	CLK_MSR_ID(129, "hdmirx_aud_clk"),
+	CLK_MSR_ID(130, "dptx_apb2"),
+	CLK_MSR_ID(131, "dptx_aud"),
+	CLK_MSR_ID(132, "audio_todptx_bclk"),
+	CLK_MSR_ID(133, "audio_txhdmitx_bclk"),
+	CLK_MSR_ID(134, "audio_txhdmitx_mclk"),
+	CLK_MSR_ID(135, "audio_txhdmitx_spdif_clk"),
+	CLK_MSR_ID(136, "mclk_0_pre"),
+	CLK_MSR_ID(137, "mclk1_0_pre"),
+	CLK_MSR_ID(138, "pixel0_pll_clkout"),
+	CLK_MSR_ID(139, "pixel1_pll_clkout"),
+	CLK_MSR_ID(140, "tcon_clk_out0"),
+	CLK_MSR_ID(141, "tcon_clk_out1"),
+	CLK_MSR_ID(142, "audio_todptx_spdif_clk"),
+	CLK_MSR_ID(143, "audio_todptx_mclk"),
+	CLK_MSR_ID(144, "dptx_lnk_clk"),
+	CLK_MSR_ID(145, "edptx_lnk_clk_tx"),
+	CLK_MSR_ID(146, "mod_audio_pdm_dclk_o_ao"),
+	CLK_MSR_ID(147, "vid2_pll"),
+	CLK_MSR_ID(151, "can1_filter"),
+	CLK_MSR_ID(152, "can0_filter"),
+	CLK_MSR_ID(153, "can1_pe"),
+	CLK_MSR_ID(154, "can0_pe"),
+	CLK_MSR_ID(155, "o_sed_clk"),
+	CLK_MSR_ID(156, "pwm_n"),
+	CLK_MSR_ID(157, "pwm_m"),
+	CLK_MSR_ID(158, "pwm_l"),
+	CLK_MSR_ID(159, "pwm_k"),
+	CLK_MSR_ID(160, "pwm_j"),
+	CLK_MSR_ID(161, "pwm_i"),
+	CLK_MSR_ID(162, "pwm_h"),
+	CLK_MSR_ID(170, "rng_ring_osc_clk[0]"),
+	CLK_MSR_ID(171, "rng_ring_osc_clk[1]"),
+	CLK_MSR_ID(172, "rng_ring_osc_clk[2]"),
+	CLK_MSR_ID(173, "rng_ring_osc_clk[3]"),
+	CLK_MSR_ID(174, "rng_ring_osc_clk[4]"),
+	CLK_MSR_ID(175, "sys_cpu_osc_ring_clk[0]"),
+	CLK_MSR_ID(176, "sys_cpu_osc_ring_clk[1]"),
+	CLK_MSR_ID(177, "sys_cpu_osc_ring_clk[2]"),
+	CLK_MSR_ID(178, "sys_cpu_osc_ring_clk[3]"),
+	CLK_MSR_ID(179, "sys_cpu_osc_ring_clk[4]"),
+	CLK_MSR_ID(180, "sys_cpu_osc_ring_clk[5]"),
+	CLK_MSR_ID(181, "sys_cpu_osc_ring_clk[6]"),
+	CLK_MSR_ID(182, "sys_cpu_osc_ring_clk[7]"),
+	CLK_MSR_ID(183, "sys_cpu_osc_ring_clk[8]"),
+	CLK_MSR_ID(184, "sys_cpu_osc_ring_clk[9]"),
+	CLK_MSR_ID(185, "osc_ring_clk_gpu[0]"),
+	CLK_MSR_ID(186, "osc_ring_clk_gpu[1]"),
+	CLK_MSR_ID(187, "osc_ring_clk_vpu"),
+	CLK_MSR_ID(188, "osc_ring_clk_dos[0]"),
+	CLK_MSR_ID(189, "osc_ring_clk_dos[1]"),
+	CLK_MSR_ID(190, "osc_ring_clk_vge"),
+	CLK_MSR_ID(191, "osc_ring_clk_nna[0]"),
+	CLK_MSR_ID(192, "osc_ring_clk_nna[1]"),
+	CLK_MSR_ID(193, "osc_ring_clk_top[0]"),
+	CLK_MSR_ID(194, "osc_ring_clk_top[1]"),
+	CLK_MSR_ID(195, "nna"),
+	CLK_MSR_ID(200, "pcie1_tl"),
+	CLK_MSR_ID(201, "pcie0_tl"),
+	CLK_MSR_ID(202, "pp"),
+	CLK_MSR_ID(203, "pwm_a(ao)"),
+	CLK_MSR_ID(204, "pwm_b(ao)"),
+	CLK_MSR_ID(205, "pwm_c(ao)"),
+	CLK_MSR_ID(206, "pwm_d(ao)"),
+	CLK_MSR_ID(207, "pwm_e(ao)"),
+	CLK_MSR_ID(208, "pwm_f(ao)"),
+	CLK_MSR_ID(209, "pwm_g(ao)"),
+	CLK_MSR_ID(210, "ao_cec"),
+	CLK_MSR_ID(211, "sec_pulse_out"),
+	CLK_MSR_ID(212, "osc_clk_out"),
+	CLK_MSR_ID(213, "earcrx_pll_clk_out"),
+	CLK_MSR_ID(215, "o_pd_sysclk"),
+	CLK_MSR_ID(216, "o_earcrx_dmac_clk"),
+	CLK_MSR_ID(217, "o_earcrx_cmdc_clk"),
+	CLK_MSR_ID(218, "o_earctx_dmac_clk"),
+	CLK_MSR_ID(219, "o_earctx_cmdc_clk"),
+	CLK_MSR_ID(220, "o_earctx_ana_dmac_clk_a2d"),
+	CLK_MSR_ID(221, "o_tohdmi_dp_tx_a_bclk"),
+	CLK_MSR_ID(222, "o_tohdmi_dp_tx_a_mclk"),
+	CLK_MSR_ID(223, "o_tohdmi_dp_tx_a_spdif_clk"),
+	CLK_MSR_ID(224, "o_tohdmi_dp_tx_b_bclk"),
+	CLK_MSR_ID(225, "o_tohdmi_dp_tx_b_mclk"),
+	CLK_MSR_ID(226, "o_tohdmi_dp_tx_b_spdif_clk"),
+	CLK_MSR_ID(227, "o_toacodec_dac_bclk"),
+	CLK_MSR_ID(228, "o_toacodec_dac_mclk"),
+	CLK_MSR_ID(229, "o_spdifout_b_mst_clk"),
+	CLK_MSR_ID(230, "o_spdifout_mst_clk"),
+	CLK_MSR_ID(231, "o_spdifin_mst_clk"),
+	CLK_MSR_ID(232, "o_audio_mclk"),
+	CLK_MSR_ID(233, "o_vad_clk"),
+	CLK_MSR_ID(234, "o_tdmout_d_sclk"),
+	CLK_MSR_ID(235, "o_tdmout_c_sclk"),
+	CLK_MSR_ID(236, "o_tdmout_b_sclk"),
+	CLK_MSR_ID(237, "o_tdmout_a_sclk"),
+	CLK_MSR_ID(238, "o_tdminb_lb_sclk"),
+	CLK_MSR_ID(239, "o_tdmin_lb_sclk"),
+	CLK_MSR_ID(240, "o_tdmin_d_sclk"),
+	CLK_MSR_ID(241, "o_tdmin_c_sclk"),
+	CLK_MSR_ID(242, "o_tdmin_b_sclk"),
+	CLK_MSR_ID(243, "o_tdmin_a_sclk"),
+	CLK_MSR_ID(244, "o_resampleb_clk"),
+	CLK_MSR_ID(245, "o_resamplea_clk"),
+	CLK_MSR_ID(246, "o_pdmb_sysclk"),
+	CLK_MSR_ID(247, "o_pdmb_dclk"),
+	CLK_MSR_ID(248, "o_pdm_sysclk"),
+	CLK_MSR_ID(249, "o_pdm_dclk"),
+	CLK_MSR_ID(250, "c_alockerb_out_clk"),
+	CLK_MSR_ID(251, "c_alockerb_in_clk"),
+	CLK_MSR_ID(252, "c_alocker_out_clk"),
+	CLK_MSR_ID(253, "c_alocker_in_clk"),
+	CLK_MSR_ID(254, "o_resample_c_clk")
+};
+
+static const struct meson_msr_id clk_msr_s6[] = {
+	CLK_MSR_ID(0, "sys_clk"),
+	CLK_MSR_ID(1, "axi_clk"),
+	CLK_MSR_ID(2, "rtc_clk"),
+	CLK_MSR_ID(3, "dspa"),
+	CLK_MSR_ID(4, "mali_stack"),
+	CLK_MSR_ID(5, "mali"),
+	CLK_MSR_ID(6, "cpu_clk_div16"),
+	CLK_MSR_ID(7, "mali_aclkm"),
+	CLK_MSR_ID(8, "cecb"),
+	CLK_MSR_ID(9, "gp2_pll"),
+	CLK_MSR_ID(10, "fclk_div5"),
+	CLK_MSR_ID(11, "p21_usb2_ckout"),
+	CLK_MSR_ID(12, "p20_usb2_ckout"),
+	CLK_MSR_ID(13, "eth_mpll_test"),
+	CLK_MSR_ID(15, "fclk_50m"),
+	CLK_MSR_ID(18, "gp1_pll"),
+	CLK_MSR_ID(19, "hifi_pll"),
+	CLK_MSR_ID(20, "gp0_pll"),
+	CLK_MSR_ID(21, "hifi1_pll"),
+	CLK_MSR_ID(22, "eth_mppll_50m_ckout"),
+	CLK_MSR_ID(23, "sys_pll_div16"),
+	CLK_MSR_ID(24, "ddr_dpll_pt_clk"),
+	CLK_MSR_ID(25, "mod_Tsin_A_CLK_IN"),
+	CLK_MSR_ID(26, "ext_Tsin_B_CLK_IN"),
+	CLK_MSR_ID(27, "mod_Tsin_C_CLK_IN"),
+	CLK_MSR_ID(28, "mod_Tsin_D_CLK_IN"),
+	CLK_MSR_ID(29, "dsi_pll_div_clk_out"),
+	CLK_MSR_ID(30, "dsi_pll_clk"),
+	CLK_MSR_ID(32, "eth_125m"),
+	CLK_MSR_ID(33, "eth_rmii"),
+	CLK_MSR_ID(34, "co_clkin_to_mac"),
+	CLK_MSR_ID(36, "co_rx_clk"),
+	CLK_MSR_ID(37, "co_tx_clk"),
+	CLK_MSR_ID(38, "eth_phy_rxclk"),
+	CLK_MSR_ID(39, "eth_phy_plltxclk"),
+	CLK_MSR_ID(40, "ephy_test_clk"),
+	CLK_MSR_ID(49, "hdmi_vx1_pix_clk"),
+	CLK_MSR_ID(50, "vid_pll"),
+	CLK_MSR_ID(51, "enci"),
+	CLK_MSR_ID(52, "encp"),
+	CLK_MSR_ID(53, "encl"),
+	CLK_MSR_ID(54, "vdac"),
+	CLK_MSR_ID(55, "cdac"),
+	CLK_MSR_ID(57, "lcd_an_clk_ph2"),
+	CLK_MSR_ID(58, "lcd_an_clk_ph3"),
+	CLK_MSR_ID(59, "hdmitx_pixel"),
+	CLK_MSR_ID(60, "vdin_meas"),
+	CLK_MSR_ID(61, "vpu"),
+	CLK_MSR_ID(62, "vpu_clkb"),
+	CLK_MSR_ID(63, "vpu_clkb_tmp"),
+	CLK_MSR_ID(64, "vpu_clkc"),
+	CLK_MSR_ID(65, "vid_lock"),
+	CLK_MSR_ID(66, "vapb"),
+	CLK_MSR_ID(67, "ge2d"),
+	CLK_MSR_ID(70, "mipi_dsi_meas"),
+	CLK_MSR_ID(71, "mipi_dsi_phy"),
+	CLK_MSR_ID(72, "mipi_csi_phy"),
+	CLK_MSR_ID(73, "csi2_adapt"),
+	CLK_MSR_ID(74, "cts_csi2_data"),
+	CLK_MSR_ID(75, "mipi_csi_phy_out"),
+	CLK_MSR_ID(76, "hdmitx_tmds"),
+	CLK_MSR_ID(77, "hdmitx_sys"),
+	CLK_MSR_ID(78, "hdmitx_fe"),
+	CLK_MSR_ID(79, "rama_clk"),
+	CLK_MSR_ID(80, "hdmitx_prif"),
+	CLK_MSR_ID(81, "hdmitx_200m"),
+	CLK_MSR_ID(82, "hdmitx_aud"),
+	CLK_MSR_ID(84, "audio_tohdmitx_mclk"),
+	CLK_MSR_ID(85, "audio_tohdmitx_bclk"),
+	CLK_MSR_ID(86, "audio_tohdmitx_lrclk"),
+	CLK_MSR_ID(87, "audio_tohdmitx_spdif_clk"),
+	CLK_MSR_ID(88, "htx_aes_clk"),
+	CLK_MSR_ID(89, "amfc"),
+	CLK_MSR_ID(93, "vdec"),
+	CLK_MSR_ID(99, "hevcf"),
+	CLK_MSR_ID(106, "deskew_pll_clk_div32_out"),
+	CLK_MSR_ID(108, "cmpr"),
+	CLK_MSR_ID(109, "dewarpa"),
+	CLK_MSR_ID(110, "sc"),
+	CLK_MSR_ID(111, "sar_adc"),
+	CLK_MSR_ID(113, "sd_emmc_c"),
+	CLK_MSR_ID(114, "sd_emmc_b"),
+	CLK_MSR_ID(115, "sd_emmc_a"),
+	CLK_MSR_ID(116, "gpio_msr_clk"),
+	CLK_MSR_ID(117, "aux_clk_o"),
+	CLK_MSR_ID(118, "spicc"),
+	CLK_MSR_ID(121, "ts"),
+	CLK_MSR_ID(130, "o_vad_clk"),
+	CLK_MSR_ID(132, "audio_locker_in_clk"),
+	CLK_MSR_ID(133, "audio_locker_out_clk"),
+	CLK_MSR_ID(134, "audio_tdmout_c_sclk"),
+	CLK_MSR_ID(135, "audio_tdmout_b_sclk"),
+	CLK_MSR_ID(136, "audio_tdmout_a_sclk"),
+	CLK_MSR_ID(137, "audio_tdmin_lb_sclk"),
+	CLK_MSR_ID(138, "audio_tdmin_c_sclk"),
+	CLK_MSR_ID(139, "audio_tdmin_b_sclk"),
+	CLK_MSR_ID(140, "audio_tdmin_a_sclk"),
+	CLK_MSR_ID(141, "audio_resamplea_clk"),
+	CLK_MSR_ID(142, "audio_pdm_sysclk"),
+	CLK_MSR_ID(143, "audio_spdifout_b_mst_clk"),
+	CLK_MSR_ID(144, "audio_spdifout_mst_clk"),
+	CLK_MSR_ID(145, "audio_spdifin_mst_clk"),
+	CLK_MSR_ID(147, "audio_resampleb_clk"),
+	CLK_MSR_ID(148, "pcie_pipe_clk"),
+	CLK_MSR_ID(149, "pcie_ref_clk"),
+	CLK_MSR_ID(150, "pcie_upcrx_cdrclk"),
+	CLK_MSR_ID(151, "pcie_upcrx_clk_sync_b20"),
+	CLK_MSR_ID(152, "pcie_u3p2pll1_clk_div16"),
+	CLK_MSR_ID(153, "pcie_u3p2pll0_clkout"),
+	CLK_MSR_ID(154, "pcie_ref_clk_p"),
+	CLK_MSR_ID(160, "pwm_j"),
+	CLK_MSR_ID(161, "pwm_i"),
+	CLK_MSR_ID(162, "pwm_h"),
+	CLK_MSR_ID(163, "pwm_g"),
+	CLK_MSR_ID(164, "pwm_f"),
+	CLK_MSR_ID(165, "pwm_e"),
+	CLK_MSR_ID(166, "pwm_d"),
+	CLK_MSR_ID(167, "pwm_c"),
+	CLK_MSR_ID(168, "pwm_b"),
+	CLK_MSR_ID(169, "pwm_a"),
+	CLK_MSR_ID(175, "rng_ring_clk[0]"),
+	CLK_MSR_ID(176, "rng_ring_clk[1]"),
+	CLK_MSR_ID(177, "rng_ring_clk[2]"),
+	CLK_MSR_ID(178, "rng_ring_clk[3]"),
+	CLK_MSR_ID(179, "rng_ring_clk[4]"),
+	CLK_MSR_ID(180, "am_ring_osc_clk_out[0]"),
+	CLK_MSR_ID(181, "am_ring_osc_clk_out[1]"),
+	CLK_MSR_ID(182, "am_ring_osc_clk_out[2]"),
+	CLK_MSR_ID(183, "am_ring_osc_clk_out[3]"),
+	CLK_MSR_ID(184, "am_ring_osc_clk_out[4]"),
+	CLK_MSR_ID(185, "am_ring_osc_clk_out[5]"),
+	CLK_MSR_ID(186, "am_ring_osc_clk_out[6]"),
+	CLK_MSR_ID(187, "am_ring_osc_clk_out[7]"),
+	CLK_MSR_ID(188, "am_ring_osc_clk_out[8]"),
+	CLK_MSR_ID(189, "am_ring_osc_clk_out[9]"),
+	CLK_MSR_ID(190, "am_ring_osc_clk_out[10]"),
+	CLK_MSR_ID(191, "am_ring_osc_clk_out[11]"),
+	CLK_MSR_ID(192, "am_ring_osc_clk_out[12]"),
+	CLK_MSR_ID(193, "am_ring_osc_clk_out[13]"),
+	CLK_MSR_ID(194, "am_ring_osc_clk_out[14]"),
+	CLK_MSR_ID(195, "am_ring_osc_clk_out[15]"),
+	CLK_MSR_ID(196, "am_ring_osc_clk_out[16]"),
+	CLK_MSR_ID(197, "nna"),
+	CLK_MSR_ID(198, "vc9000e_axi"),
+	CLK_MSR_ID(199, "vc9000e_core"),
+	CLK_MSR_ID(201, "pcie_tl"),
+	CLK_MSR_ID(204, "u3p2pll1_clk_div16"),
+	CLK_MSR_ID(205, "u3p2pll0_clkout"),
+	CLK_MSR_ID(206, "upctx_clk_sync_b20"),
+	CLK_MSR_ID(207, "upcrx_carclk"),
+	CLK_MSR_ID(208, "usb_pipe_clk"),
+	CLK_MSR_ID(209, "earcrx_pll_out"),
+	CLK_MSR_ID(210, "mclk_pll_clk")
+};
+
+static const struct meson_msr_id clk_msr_s7[] = {
+	CLK_MSR_ID(0, "sys_clk"),
+	CLK_MSR_ID(1, "axi_clk"),
+	CLK_MSR_ID(2, "rtc_clk"),
+	CLK_MSR_ID(5, "mali"),
+	CLK_MSR_ID(6, "cpu_clk_div16"),
+	CLK_MSR_ID(8, "cecb"),
+	CLK_MSR_ID(10, "fclk_div5"),
+	CLK_MSR_ID(11, "p21_usb2_ckout"),
+	CLK_MSR_ID(12, "p20_usb2_ckout"),
+	CLK_MSR_ID(13, "eth_mpll_test"),
+	CLK_MSR_ID(15, "fclk_50m"),
+	CLK_MSR_ID(18, "gp1_pll"),
+	CLK_MSR_ID(19, "hifi_pll"),
+	CLK_MSR_ID(20, "gp0_pll"),
+	CLK_MSR_ID(21, "hifi1_pll"),
+	CLK_MSR_ID(22, "eth_mppll_50m_ckout"),
+	CLK_MSR_ID(23, "sys_pll_div16"),
+	CLK_MSR_ID(24, "ddr_dpll_pt_clk"),
+	CLK_MSR_ID(25, "mod_Tsin_A_CLK_IN"),
+	CLK_MSR_ID(32, "eth_125m"),
+	CLK_MSR_ID(33, "eth_rmii"),
+	CLK_MSR_ID(34, "co_clkin_to_mac"),
+	CLK_MSR_ID(36, "co_rx_clk"),
+	CLK_MSR_ID(37, "co_tx_clk"),
+	CLK_MSR_ID(38, "eth_phy_rxclk"),
+	CLK_MSR_ID(39, "eth_phy_plltxclk"),
+	CLK_MSR_ID(40, "ephy_test_clk"),
+	CLK_MSR_ID(49, "hdmi_vx1_pix_clk"),
+	CLK_MSR_ID(50, "vid_pll"),
+	CLK_MSR_ID(51, "enci"),
+	CLK_MSR_ID(52, "encp"),
+	CLK_MSR_ID(53, "encl"),
+	CLK_MSR_ID(54, "vdac"),
+	CLK_MSR_ID(55, "cdac"),
+	CLK_MSR_ID(57, "lcd_an_clk_ph2"),
+	CLK_MSR_ID(58, "lcd_an_clk_ph3"),
+	CLK_MSR_ID(59, "hdmitx_pixel"),
+	CLK_MSR_ID(60, "vdin_meas"),
+	CLK_MSR_ID(61, "vpu"),
+	CLK_MSR_ID(62, "vpu_clkb"),
+	CLK_MSR_ID(63, "vpu_clkb_tmp"),
+	CLK_MSR_ID(64, "vpu_clkc"),
+	CLK_MSR_ID(65, "vid_lock"),
+	CLK_MSR_ID(66, "vapb"),
+	CLK_MSR_ID(67, "ge2d"),
+	CLK_MSR_ID(76, "hdmitx_tmds"),
+	CLK_MSR_ID(77, "hdmitx_sys"),
+	CLK_MSR_ID(78, "hdmitx_fe"),
+	CLK_MSR_ID(80, "hdmitx_prif"),
+	CLK_MSR_ID(81, "hdmitx_200m"),
+	CLK_MSR_ID(82, "hdmitx_aud"),
+	CLK_MSR_ID(84, "audio_tohdmitx_mclk"),
+	CLK_MSR_ID(85, "audio_tohdmitx_bclk"),
+	CLK_MSR_ID(86, "audio_tohdmitx_lrclk"),
+	CLK_MSR_ID(87, "audio_tohdmitx_spdif_clk"),
+	CLK_MSR_ID(88, "htx_aes_clk"),
+	CLK_MSR_ID(93, "vdec"),
+	CLK_MSR_ID(99, "hevcf"),
+	CLK_MSR_ID(106, "deskew_pll_clk_div32_out"),
+	CLK_MSR_ID(110, "sc"),
+	CLK_MSR_ID(111, "sar_adc"),
+	CLK_MSR_ID(113, "sd_emmc_c"),
+	CLK_MSR_ID(114, "sd_emmc_b"),
+	CLK_MSR_ID(115, "sd_emmc_a"),
+	CLK_MSR_ID(116, "gpio_msr_clk"),
+	CLK_MSR_ID(118, "spicc"),
+	CLK_MSR_ID(121, "ts"),
+	CLK_MSR_ID(130, "o_vad_clk"),
+	CLK_MSR_ID(131, "au_dac_clk_x128"),
+	CLK_MSR_ID(132, "audio_locker_in_clk"),
+	CLK_MSR_ID(133, "audio_locker_out_clk"),
+	CLK_MSR_ID(134, "audio_tdmout_c_sclk"),
+	CLK_MSR_ID(135, "audio_tdmout_b_sclk"),
+	CLK_MSR_ID(136, "audio_tdmout_a_sclk"),
+	CLK_MSR_ID(137, "audio_tdmin_lb_sclk"),
+	CLK_MSR_ID(138, "audio_tdmin_c_sclk"),
+	CLK_MSR_ID(139, "audio_tdmin_b_sclk"),
+	CLK_MSR_ID(140, "audio_tdmin_a_sclk"),
+	CLK_MSR_ID(141, "audio_resamplea_clk"),
+	CLK_MSR_ID(142, "audio_pdm_sysclk"),
+	CLK_MSR_ID(143, "audio_spdifout_b_mst_clk"),
+	CLK_MSR_ID(144, "audio_spdifout_mst_clk"),
+	CLK_MSR_ID(145, "audio_spdifin_mst_clk"),
+	CLK_MSR_ID(147, "audio_resampleb_clk"),
+	CLK_MSR_ID(160, "pwm_j"),
+	CLK_MSR_ID(161, "pwm_i"),
+	CLK_MSR_ID(162, "pwm_h"),
+	CLK_MSR_ID(163, "pwm_g"),
+	CLK_MSR_ID(164, "pwm_f"),
+	CLK_MSR_ID(165, "pwm_e"),
+	CLK_MSR_ID(166, "pwm_d"),
+	CLK_MSR_ID(167, "pwm_c"),
+	CLK_MSR_ID(168, "pwm_b"),
+	CLK_MSR_ID(169, "pwm_a"),
+	CLK_MSR_ID(176, "rng_ring_clk[0]"),
+	CLK_MSR_ID(177, "rng_ring_clk[1]"),
+	CLK_MSR_ID(178, "rng_ring_clk[2]"),
+	CLK_MSR_ID(179, "rng_ring_clk[3]"),
+	CLK_MSR_ID(180, "osc_ring_clk[0](a55 core0 14_slvt)"),
+	CLK_MSR_ID(181, "osc_ring_clk[1](a55 core1 14_slvt)"),
+	CLK_MSR_ID(182, "osc_ring_clk[2](a55 core2 14_slvt)"),
+	CLK_MSR_ID(183, "osc_ring_clk[3](a55 core3 14_slvt)"),
+	CLK_MSR_ID(184, "osc_ring_clk[4](a55_pwr[0] 16_slvt)"),
+	CLK_MSR_ID(185, "osc_ring_clk[5](a55_pwr[1] 14_lvt)"),
+	CLK_MSR_ID(186, "osc_ring_clk[6](a55_pwr[2] 14_rvt)"),
+	CLK_MSR_ID(187, "osc_ring_clk[7](mali[1] 14_lvt)"),
+	CLK_MSR_ID(188, "osc_ring_clk[8](mali[1] 14_rvt)"),
+	CLK_MSR_ID(189, "osc_ring_clk[9](dos[0] 16_lvt)"),
+	CLK_MSR_ID(190, "osc_ring_clk[10](dos[1] 14_rvt)"),
+	CLK_MSR_ID(191, "osc_ring_clk[11](ddr[0] 9t_14_lvt)"),
+	CLK_MSR_ID(192, "osc_ring_clk[12](top[0] 16_rvt)"),
+};
+
+static const struct meson_msr_id clk_msr_s7d[] = {
+	CLK_MSR_ID(0, "sys_clk"),
+	CLK_MSR_ID(1, "axi_clk"),
+	CLK_MSR_ID(2, "rtc_clk"),
+	CLK_MSR_ID(4, "mali_stack"),
+	CLK_MSR_ID(5, "mali"),
+	CLK_MSR_ID(6, "cpu_clk_div16"),
+	CLK_MSR_ID(8, "cecb"),
+	CLK_MSR_ID(9, "mali_aclkm"),
+	CLK_MSR_ID(10, "fclk_div5"),
+	CLK_MSR_ID(11, "p21_usb2_ckout"),
+	CLK_MSR_ID(12, "p20_usb2_ckout"),
+	CLK_MSR_ID(13, "eth_mpll_test"),
+	CLK_MSR_ID(15, "fclk_50m"),
+	CLK_MSR_ID(18, "gp1_pll"),
+	CLK_MSR_ID(19, "hifi_pll"),
+	CLK_MSR_ID(20, "gp0_pll"),
+	CLK_MSR_ID(21, "hifi1_pll"),
+	CLK_MSR_ID(22, "eth_mppll_50m_ckout"),
+	CLK_MSR_ID(23, "sys_pll_div16"),
+	CLK_MSR_ID(24, "ddr_dpll_pt_clk"),
+	CLK_MSR_ID(25, "mod_Tsin_A_CLK_IN"),
+	CLK_MSR_ID(26, "mod_Tsin_B_CLK_IN"),
+	CLK_MSR_ID(31, "earcrx_pll_clk_out"),
+	CLK_MSR_ID(32, "eth_125m"),
+	CLK_MSR_ID(33, "eth_rmii"),
+	CLK_MSR_ID(34, "co_clkin_to_mac"),
+	CLK_MSR_ID(36, "co_rx_clk"),
+	CLK_MSR_ID(37, "co_tx_clk"),
+	CLK_MSR_ID(38, "eth_phy_rxclk"),
+	CLK_MSR_ID(39, "eth_phy_plltxclk"),
+	CLK_MSR_ID(40, "ephy_test_clk"),
+	CLK_MSR_ID(49, "hdmi_vx1_pix_clk"),
+	CLK_MSR_ID(50, "vid_pll"),
+	CLK_MSR_ID(51, "enci"),
+	CLK_MSR_ID(52, "encp"),
+	CLK_MSR_ID(53, "encl"),
+	CLK_MSR_ID(54, "vdac"),
+	CLK_MSR_ID(55, "cdac"),
+	CLK_MSR_ID(57, "lcd_an_clk_ph2"),
+	CLK_MSR_ID(58, "lcd_an_clk_ph3"),
+	CLK_MSR_ID(59, "hdmitx_pixel"),
+	CLK_MSR_ID(60, "vdin_meas"),
+	CLK_MSR_ID(61, "vpu"),
+	CLK_MSR_ID(62, "vpu_clkb"),
+	CLK_MSR_ID(63, "vpu_clkb_tmp"),
+	CLK_MSR_ID(64, "vpu_clkc"),
+	CLK_MSR_ID(65, "vid_lock"),
+	CLK_MSR_ID(66, "vapb"),
+	CLK_MSR_ID(67, "ge2d"),
+	CLK_MSR_ID(76, "hdmitx_tmds"),
+	CLK_MSR_ID(77, "hdmitx_sys"),
+	CLK_MSR_ID(78, "hdmitx_fe"),
+	CLK_MSR_ID(80, "hdmitx_prif"),
+	CLK_MSR_ID(81, "hdmitx_200m"),
+	CLK_MSR_ID(82, "hdmitx_aud"),
+	CLK_MSR_ID(84, "audio_tohdmitx_mclk"),
+	CLK_MSR_ID(85, "audio_tohdmitx_bclk"),
+	CLK_MSR_ID(86, "audio_tohdmitx_lrclk"),
+	CLK_MSR_ID(87, "audio_tohdmitx_spdif_clk"),
+	CLK_MSR_ID(88, "htx_aes_clk"),
+	CLK_MSR_ID(89, "amfc"),
+	CLK_MSR_ID(93, "vdec"),
+	CLK_MSR_ID(97, "hcodec"),
+	CLK_MSR_ID(99, "hevcf"),
+	CLK_MSR_ID(106, "deskew_pll_clk_div32_out"),
+	CLK_MSR_ID(110, "sc"),
+	CLK_MSR_ID(111, "sar_adc"),
+	CLK_MSR_ID(112, "aux_adc_clk_to_gpio"),
+	CLK_MSR_ID(113, "sd_emmc_c"),
+	CLK_MSR_ID(114, "sd_emmc_b"),
+	CLK_MSR_ID(115, "sd_emmc_a"),
+	CLK_MSR_ID(116, "gpio_msr_clk"),
+	CLK_MSR_ID(117, "aux_clk_o"),
+	CLK_MSR_ID(118, "spicc"),
+	CLK_MSR_ID(121, "ts"),
+	CLK_MSR_ID(130, "o_vad_clk"),
+	CLK_MSR_ID(131, "au_dac_clk_x128"),
+	CLK_MSR_ID(132, "audio_locker_in_clk"),
+	CLK_MSR_ID(133, "audio_locker_out_clk"),
+	CLK_MSR_ID(134, "audio_tdmout_c_sclk"),
+	CLK_MSR_ID(135, "audio_tdmout_b_sclk"),
+	CLK_MSR_ID(136, "audio_tdmout_a_sclk"),
+	CLK_MSR_ID(137, "audio_tdmin_lb_sclk"),
+	CLK_MSR_ID(138, "audio_tdmin_c_sclk"),
+	CLK_MSR_ID(139, "audio_tdmin_b_sclk"),
+	CLK_MSR_ID(140, "audio_tdmin_a_sclk"),
+	CLK_MSR_ID(141, "audio_resamplea_clk"),
+	CLK_MSR_ID(142, "audio_pdm_sysclk"),
+	CLK_MSR_ID(143, "audio_spdifout_b_mst_clk"),
+	CLK_MSR_ID(144, "audio_spdifout_mst_clk"),
+	CLK_MSR_ID(145, "audio_spdifin_mst_clk"),
+	CLK_MSR_ID(146, "mod_audio_pdm_dclk_o"),
+	CLK_MSR_ID(147, "audio_resampleb_clk"),
+	CLK_MSR_ID(160, "pwm_j"),
+	CLK_MSR_ID(161, "pwm_i"),
+	CLK_MSR_ID(162, "pwm_h"),
+	CLK_MSR_ID(163, "pwm_g"),
+	CLK_MSR_ID(164, "pwm_f"),
+	CLK_MSR_ID(165, "pwm_e"),
+	CLK_MSR_ID(166, "pwm_d"),
+	CLK_MSR_ID(167, "pwm_c"),
+	CLK_MSR_ID(168, "pwm_b"),
+	CLK_MSR_ID(169, "pwm_a"),
+	CLK_MSR_ID(176, "rng_ring_clk[0]"),
+	CLK_MSR_ID(177, "rng_ring_clk[1]"),
+	CLK_MSR_ID(178, "rng_ring_clk[2]"),
+	CLK_MSR_ID(179, "rng_ring_clk[3]"),
+	CLK_MSR_ID(180, "osc_ring_clk[0](a55 core0 14_slvt)"),
+	CLK_MSR_ID(181, "osc_ring_clk[1](a55 core1 14_slvt)"),
+	CLK_MSR_ID(182, "osc_ring_clk[2](a55 core2 14_slvt)"),
+	CLK_MSR_ID(183, "osc_ring_clk[3](a55 core3 14_slvt)"),
+	CLK_MSR_ID(184, "osc_ring_clk[4](a55_pwr[0] 16_slvt)"),
+	CLK_MSR_ID(185, "osc_ring_clk[5](a55_pwr[1] 14_lvt)"),
+	CLK_MSR_ID(186, "osc_ring_clk[6](a55_pwr[2] 14_rvt)"),
+	CLK_MSR_ID(187, "osc_ring_clk[7](mali[1] 14_lvt)"),
+	CLK_MSR_ID(188, "osc_ring_clk[8](mali[1] 14_rvt)"),
+	CLK_MSR_ID(189, "osc_ring_clk[9](dos[0] 16_lvt)"),
+	CLK_MSR_ID(190, "osc_ring_clk[10](dos[1] 14_rvt)"),
+	CLK_MSR_ID(191, "osc_ring_clk[11](ddr[0] 9t_14_lvt)"),
+	CLK_MSR_ID(192, "osc_ring_clk[12](top[0] 16_rvt)"),
+};
+
 static int meson_measure_id(struct meson_msr_id *clk_msr_id,
 			    unsigned int duration)
 {
@@ -1285,6 +2122,24 @@ static const struct meson_msr_data clk_msr_a1_data = {
 	.reg = &msr_reg_offset_v2,
 };
 
+static const struct meson_msr_data clk_msr_a4_data = {
+	.msr_table = (void *)clk_msr_a4,
+	.msr_count = ARRAY_SIZE(clk_msr_a4),
+	.reg = &msr_reg_offset_v2,
+};
+
+static const struct meson_msr_data clk_msr_a5_data = {
+	.msr_table = (void *)clk_msr_a5,
+	.msr_count = ARRAY_SIZE(clk_msr_a5),
+	.reg = &msr_reg_offset_v2,
+};
+
+static const struct meson_msr_data clk_msr_a9_data = {
+	.msr_table = (void *)clk_msr_a9,
+	.msr_count = ARRAY_SIZE(clk_msr_a9),
+	.reg = &msr_reg_offset_v2,
+};
+
 static const struct meson_msr_data clk_msr_c3_data = {
 	.msr_table = (void *)clk_msr_c3,
 	.msr_count = ARRAY_SIZE(clk_msr_c3),
@@ -1297,6 +2152,24 @@ static const struct meson_msr_data clk_msr_s4_data = {
 	.reg = &msr_reg_offset_v2,
 };
 
+static const struct meson_msr_data clk_msr_s6_data = {
+	.msr_table = (void *)clk_msr_s6,
+	.msr_count = ARRAY_SIZE(clk_msr_s6),
+	.reg = &msr_reg_offset_v2,
+};
+
+static const struct meson_msr_data clk_msr_s7_data = {
+	.msr_table = (void *)clk_msr_s7,
+	.msr_count = ARRAY_SIZE(clk_msr_s7),
+	.reg = &msr_reg_offset_v2,
+};
+
+static const struct meson_msr_data clk_msr_s7d_data = {
+	.msr_table = (void *)clk_msr_s7d,
+	.msr_count = ARRAY_SIZE(clk_msr_s7d),
+	.reg = &msr_reg_offset_v2,
+};
+
 static const struct meson_msr_data clk_msr_t7_data = {
 	.msr_table = (void *)clk_msr_t7,
 	.msr_count = ARRAY_SIZE(clk_msr_t7),
@@ -1308,6 +2181,18 @@ static const struct of_device_id meson_msr_match_table[] = {
 		.compatible = "amlogic,a1-clk-measure",
 		.data = &clk_msr_a1_data,
 	},
+	{
+		.compatible = "amlogic,a4-clk-measure",
+		.data = &clk_msr_a4_data,
+	},
+	{
+		.compatible = "amlogic,a5-clk-measure",
+		.data = &clk_msr_a5_data,
+	},
+	{
+		.compatible = "amlogic,a9-clk-measure",
+		.data = &clk_msr_a9_data,
+	},
 	{
 		.compatible = "amlogic,c3-clk-measure",
 		.data = &clk_msr_c3_data,
@@ -1340,6 +2225,18 @@ static const struct of_device_id meson_msr_match_table[] = {
 		.compatible = "amlogic,s4-clk-measure",
 		.data = &clk_msr_s4_data,
 	},
+	{
+		.compatible = "amlogic,s6-clk-measure",
+		.data = &clk_msr_s6_data,
+	},
+	{
+		.compatible = "amlogic,s7-clk-measure",
+		.data = &clk_msr_s7_data,
+	},
+	{
+		.compatible = "amlogic,s7d-clk-measure",
+		.data = &clk_msr_s7d_data,
+	},
 	{
 		.compatible = "amlogic,t7-clk-measure",
 		.data = &clk_msr_t7_data,

-- 
2.42.0



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[PATCH v2 06/12] soc: amlogic: clk-measure: Optimize CLK_MSR_ID to reduce memory usage

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

The original CLK_MSR_ID macro uses __id as the designated array index.
This can waste memory when defining struct meson_msr_id arrays. For
example:

    static const struct meson_msr_id clk_msr_foo[] = {
        CLK_MSR_ID(255, NULL),
    };

Although the array contains only one valid entry, it occupies space for
256 elements because the designated initializer forces the array size to
match the highest index.

The driver does not rely on the array index when accessing measurement
IDs. Instead, the measurement ID is obtained from the id field of struct
meson_msr_id. Therefore, removing the designated array index from
CLK_MSR_ID does not affect the current driver behavior while
significantly reducing unnecessary memory usage.

Compared with before and after modification, the memory size is reduced
by 24.76%:
$ scripts/bloat-o-meter pre_meson-clk-measure.o meson-clk-measure.o
add/remove: 0/0 grow/shrink: 0/15 up/down: 0/-16224 (-16224)
Function                                     old     new   delta
clk_msr_sm1                                 3072    3048     -24
clk_msr_a1                                  1488    1272    -216
clk_msr_g12a                                2952    2712    -240
clk_msr_gx                                  1992    1608    -384
clk_msr_m8                                  1536    1104    -432
clk_msr_a9                                  6120    5544    -576
clk_msr_t7                                  5352    4632    -720
clk_msr_axg                                 2640    1704    -936
clk_msr_s6                                  5064    3672   -1392
clk_msr_c3                                  4896    3264   -1632
clk_msr_s7d                                 4632    2880   -1752
clk_msr_s4                                  5376    3576   -1800
clk_msr_a4                                  4488    2544   -1944
clk_msr_s7                                  4632    2664   -1968
clk_msr_a5                                  4560    2352   -2208
Total: Before=65527, After=49303, chg -24.76%

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 drivers/soc/amlogic/meson-clk-measure.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c
index 50928ac14f86..33767f0bc67c 100644
--- a/drivers/soc/amlogic/meson-clk-measure.c
+++ b/drivers/soc/amlogic/meson-clk-measure.c
@@ -55,7 +55,7 @@ struct meson_msr {
 };
 
 #define CLK_MSR_ID(__id, __name) \
-	[__id] = {.id = __id, .name = __name,}
+	{.id = __id, .name = __name,}
 
 static const struct meson_msr_id clk_msr_m8[] = {
 	CLK_MSR_ID(0, "ring_osc_out_ee0"),

-- 
2.42.0



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[PATCH v2 07/12] arm64: dts: amlogic: a5: Add clk-measure controller node

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Add the clk-measure controller node for A5 SoC family.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
index 2b12d8284594..0be176ace337 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -157,4 +157,9 @@ gpio_intc: interrupt-controller@4080 {
 		amlogic,channel-interrupts =
 			<10 11 12 13 14 15 16 17 18 19 20 21>;
 	};
+
+	clk_msr: clock-measure@48000 {
+		compatible = "amlogic,a5-clk-measure";
+		reg = <0x0 0x48000 0x0 0x1c>;
+	};
 };

-- 
2.42.0



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[PATCH v2 08/12] arm64: dts: amlogic: a4: Add clk-measure controller node

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Add the clk-measure controller node for A4 SoC family.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index fce45933fa28..762754b33f23 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -207,6 +207,11 @@ gpio_intc: interrupt-controller@4080 {
 			<10 11 12 13 14 15 16 17 18 19 20 21>;
 	};
 
+	clk_msr: clock-measure@48000 {
+		compatible = "amlogic,a4-clk-measure";
+		reg = <0x0 0x48000 0x0 0x1c>;
+	};
+
 	ao_pinctrl: pinctrl@8e700 {
 		compatible = "amlogic,pinctrl-a4";
 		#address-cells = <2>;

-- 
2.42.0



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[PATCH v2 09/12] arm64: dts: amlogic: s7: Add clk-measure controller node

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Add the clk-measure controller node for S7 SoC family.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
index a3faf4d188e1..64440df4f542 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
@@ -239,6 +239,11 @@ ao-secure@10220 {
 				reg = <0x0 0x10220 0x0 0x140>;
 				amlogic,has-chip-id;
 			};
+
+			clk_msr: clock-measure@48000 {
+				compatible = "amlogic,s7-clk-measure";
+				reg = <0x0 0x48000 0x0 0x1c>;
+			};
 		};
 	};
 };

-- 
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[PATCH v2 10/12] arm64: dts: amlogic: s7d: Add clk-measure controller node

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Add the clk-measure controller node for S7D SoC family.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi
index 0c4417bcd682..5593ff9e07eb 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi
@@ -212,6 +212,11 @@ ao-secure@10220 {
 				reg = <0x0 0x10220 0x0 0x140>;
 				amlogic,has-chip-id;
 			};
+
+			clk_msr: clock-measure@48000 {
+				compatible = "amlogic,s7d-clk-measure";
+				reg = <0x0 0x48000 0x0 0x1c>;
+			};
 		};
 	};
 };

-- 
2.42.0



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[PATCH v2 11/12] arm64: dts: amlogic: s6: Add clk-measure controller node

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Add the clk-measure controller node for S6 SoC family.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
index ab3acef2b147..b0a1a05297ce 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
@@ -217,6 +217,11 @@ ao-secure@10220 {
 				reg = <0x0 0x10220 0x0 0x140>;
 				amlogic,has-chip-id;
 			};
+
+			clk_msr: clock-measure@48000 {
+				compatible = "amlogic,s6-clk-measure";
+				reg = <0x0 0x48000 0x0 0x1c>;
+			};
 		};
 	};
 };

-- 
2.42.0



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[PATCH v2 12/12] arm64: dts: amlogic: a9: Add clk-measure controller node

[Chuan Liu via B4 Relay]

From: Chuan Liu <chuan.liu@amlogic.com>

Add the clk-measure controller node for A9 SoC family.

Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi
index b0e0fadeed82..91f4cf319b0d 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi
@@ -185,6 +185,11 @@ gpio_intc: interrupt-controller@4080 {
 				amlogic,channel-interrupts =
 					<10 11 12 13 14 15 16 17 18 19 20 21>;
 			};
+
+			clk_msr: clock-measure@48000 {
+				compatible = "amlogic,a9-clk-measure";
+				reg = <0x0 0x48000 0x0 0x1c>;
+			};
 		};
 
 		gic: interrupt-controller@ff800000 {

-- 
2.42.0



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Re: [PATCH v2 00/12] soc: amlogic: clk-measure: Add support for more SoCs

[Neil Armstrong]

On 9/20/26 12:25, Chuan Liu via B4 Relay wrote:
> This patch series adds clk-measure support for the Amlogic A5, A4, S7,
> S7D, S6 and A9 SoCs, listed in the order of their release.
> 
> The clock names for the clk-measure channels are kept consistent with
> those used by the clock driver as much as possible, making it easier to
> identify the relationship between the clk-measure channels and the
> corresponding clocks in the clock driver.
> 
> This patchset also includes an additional patch to optimize memory usage:
>    - soc: amlogic: clk-measure: Optimize CLK_MSR_ID to reduce memory usage
> 
> To avoid requiring everyone to spend additional effort on a separate
> patchset, I have included it in this series. Please feel free to point
> out if this is not appropriate for this series.
> 
> To improve maintainability, this patchset also includes a patch to reorder
> the dt-binding and the compatible entries in the driver.
> 
> To minimize unrelated changes, the existing clk-measure channel tables in
> the driver are left in their original order. The tables for the newly
> supported SoCs are ordered alphabetically.
> 
> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
> ---
> Changes in v2:
> - Reorder the dt-binding and the compatible entries in the driver
>    alphabetically.
> - Order the clk-measure channel tables for the newly supported SoCs
>    alphabetically.
> - Add the const qualifier to the A9 clk-measure channel table.
> - Rename "exit_Tsin_B_CLK_IN" to "ext_Tsin_B_CLK_IN" in the A9 clk-measure
>    channel table.
> - Link to v1: https://lore.kernel.org/r/20260911-more-socs-to-support-clk_measure-v1-0-940e269aa52f@amlogic.com
> 
> ---
> Chuan Liu (12):
>        dt-bindings: soc: amlogic: Reordering compatible of clk-measure
>        dt-bindings: soc: amlogic: Add clk-measure compatible to support more SoCs
>        soc: amlogic: clk-measure: Support more measurement channels
>        soc: amlogic: clk-measure: Align compatible entries with DT bindings
>        soc: amlogic: clk-measure: Add support for more SoCs
>        soc: amlogic: clk-measure: Optimize CLK_MSR_ID to reduce memory usage
>        arm64: dts: amlogic: a5: Add clk-measure controller node
>        arm64: dts: amlogic: a4: Add clk-measure controller node
>        arm64: dts: amlogic: s7: Add clk-measure controller node
>        arm64: dts: amlogic: s7d: Add clk-measure controller node
>        arm64: dts: amlogic: s6: Add clk-measure controller node
>        arm64: dts: amlogic: a9: Add clk-measure controller node
> 
>   .../soc/amlogic/amlogic,meson-gx-clk-measure.yaml  |  16 +-
>   arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi        |   5 +
>   arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi        |   5 +
>   arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi        |   5 +
>   arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi        |   5 +
>   arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi        |   5 +
>   arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi       |   5 +
>   drivers/soc/amlogic/meson-clk-measure.c            | 927 ++++++++++++++++++++-
>   8 files changed, 953 insertions(+), 20 deletions(-)
> ---
> base-commit: a2530c83c458a503e55219966217dfd1c36a385e
> change-id: 20260710-more-socs-to-support-clk_measure-c826f8ab9e68
> 
> Best regards,

For the whole serie:
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil

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