Re: [PATCH 02/10] arm64: dts: amlogic: meson-s4: describe the CPU caches

[neil.armstrong@linaro.org]

On 11/6/26 11:46, christian.koever-draxl@student.uibk.ac.at wrote:
> From: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
> 
> Describe the per-core L1 caches and the shared 512 KiB L2 cache, with
> the geometry the cores report in CCSIDR_EL1 on an S905W2.
> 
> Signed-off-by: Christian Stefan Kövér-Draxl <ckoever@outlook.de>
> ---
>   arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 38 +++++++++++++++++++++++
>   1 file changed, 38 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> index 2a6fbd530836..675db02a8d5e 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> @@ -22,6 +22,13 @@ cpu0: cpu@0 {
>   			compatible = "arm,cortex-a35";
>   			reg = <0x0 0x0>;
>   			enable-method = "psci";
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <128>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
>   		};
>   
>   		cpu1: cpu@1 {
> @@ -29,6 +36,13 @@ cpu1: cpu@1 {
>   			compatible = "arm,cortex-a35";
>   			reg = <0x0 0x1>;
>   			enable-method = "psci";
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <128>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
>   		};
>   
>   		cpu2: cpu@2 {
> @@ -36,6 +50,13 @@ cpu2: cpu@2 {
>   			compatible = "arm,cortex-a35";
>   			reg = <0x0 0x2>;
>   			enable-method = "psci";
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <128>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
>   		};
>   
>   		cpu3: cpu@3 {
> @@ -43,6 +64,23 @@ cpu3: cpu@3 {
>   			compatible = "arm,cortex-a35";
>   			reg = <0x0 0x3>;
>   			enable-method = "psci";
> +			d-cache-line-size = <64>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <128>;
> +			i-cache-line-size = <64>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <256>;
> +			next-level-cache = <&l2>;
> +		};
> +
> +		/* Geometry as CCSIDR_EL1 reports it on S905W2. */
> +		l2: l2-cache0 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +			cache-size = <0x80000>; /* L2. 512 KB */
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
>   		};
>   	};
>   

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic