[PATCH v7 0/3] PCI: Refactor PCIe speed validation and conversion functions

[PATCH v7 0/3] PCI: Refactor PCIe speed validation and conversion functions

[Hans Zhang]

This series refactors PCIe speed validation and conversion logic to
shared functions in the public header, eliminating code duplication
and ensuring consistency across drivers.

---
Changes for v7:
- patch 0002 add #include <asm/bug.h> (Ilpo)
- s/u32 link_speed/enum pci_bus_speed link_speed/ (Ilpo)
- The return value of pci_bus_speed2lnkctl2 uses the variable ctrl2_speed
  to avoid the abuse of variable types. (Ilpo)

Changes for v6:
https://patchwork.kernel.org/project/linux-pci/patch/20260406105613.1228673-1-18255117159@163.com/

- missing one line of code:
  link_speed = pcie_get_link_speed(pci->max_link_speed); 

Changes for v5:
https://patchwork.kernel.org/project/linux-pci/patch/20260406104708.1218648-1-18255117159@163.com/

- Rebase to v7.0-rc1. (pci/next tree)

Changes for v4:
https://patchwork.kernel.org/project/linux-pci/patch/20251102143206.111347-1-18255117159@163.com/

- Maintain O(1) array-based lookup for speed conversion (addressing
  performance concerns from v3 feedback)
- Move pcie_valid_speed() and pci_bus_speed2lnkctl2() to pci.h
- Update dwc driver to use the shared functions
- Rebase to v6.18-rc3.

This addresses the feedback from Lukas Wunner and Manivannan Sadhasivam
on the v3 submission, ensuring no runtime performance regression while
achieving code reuse.

Changes for v3:
https://patchwork.kernel.org/project/linux-pci/patch/20250816154633.338653-1-18255117159@163.com/

- Rebase to v6.17-rc1.
- Gentle ping.

Changes for v2:
- s/PCIE_SPEED2LNKCTL2_TLS_ENC/PCIE_SPEED2LNKCTL2_TLS
- The patch commit message were modified.
---

Hans Zhang (3):
  PCI: Add public pcie_valid_speed() for shared validation
  PCI: Move pci_bus_speed2lnkctl2() to public header
  PCI: dwc: Use common speed conversion function

 drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------
 drivers/pci/pci.h                            | 23 ++++++++++++++++
 drivers/pci/pcie/bwctrl.c                    | 22 ---------------
 3 files changed, 32 insertions(+), 41 deletions(-)


base-commit: 525e91d84dc085492b36d4b87abb7c1cc93fcb44
-- 
2.34.1

[PATCH v7 1/3] PCI: Add public pcie_valid_speed() for shared validation

[Hans Zhang]

Extract the PCIe speed validation logic from bwctrl.c's static
pcie_valid_speed() into a public static inline function in pci.h.

This allows consistent speed range checks (2.5GT/s to 64.0GT/s) across
multiple drivers and functions, avoiding duplicate code and ensuring
validation consistency as per PCIe specifications.

Signed-off-by: Hans Zhang <18255117159@163.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
---
 drivers/pci/pci.h         | 5 +++++
 drivers/pci/pcie/bwctrl.c | 5 -----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4a14f88e543a..f0a082bfd6f1 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -606,6 +606,11 @@ void pci_bus_put(struct pci_bus *bus);
 	 (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
 	 0)
 
+static inline bool pcie_valid_speed(enum pci_bus_speed speed)
+{
+	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
+}
+
 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
 {
 	switch (speed) {
diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
index c4c8d260bf96..ea82e326f164 100644
--- a/drivers/pci/pcie/bwctrl.c
+++ b/drivers/pci/pcie/bwctrl.c
@@ -48,11 +48,6 @@ struct pcie_bwctrl_data {
 /* Prevent port removal during Link Speed changes. */
 static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
 
-static bool pcie_valid_speed(enum pci_bus_speed speed)
-{
-	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
-}
-
 static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
 {
 	static const u8 speed_conv[] = {
-- 
2.34.1

Re: [PATCH v7 1/3] PCI: Add public pcie_valid_speed() for shared validation

[Bjorn Helgaas]

On Tue, Apr 07, 2026 at 09:04:48PM +0800, Hans Zhang wrote:
> Extract the PCIe speed validation logic from bwctrl.c's static
> pcie_valid_speed() into a public static inline function in pci.h.
> 
> This allows consistent speed range checks (2.5GT/s to 64.0GT/s) across
> multiple drivers and functions, avoiding duplicate code and ensuring
> validation consistency as per PCIe specifications.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

Any objection, Ilpo?

It looks like 1/3 and 2/3 are pure moves, and the interesting part is
the use in dwc, which I'd like to be reviewed and applied by Mani.

> ---
>  drivers/pci/pci.h         | 5 +++++
>  drivers/pci/pcie/bwctrl.c | 5 -----
>  2 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 4a14f88e543a..f0a082bfd6f1 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -606,6 +606,11 @@ void pci_bus_put(struct pci_bus *bus);
>  	 (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
>  	 0)
>  
> +static inline bool pcie_valid_speed(enum pci_bus_speed speed)
> +{
> +	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
> +}
> +
>  static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
>  {
>  	switch (speed) {
> diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
> index c4c8d260bf96..ea82e326f164 100644
> --- a/drivers/pci/pcie/bwctrl.c
> +++ b/drivers/pci/pcie/bwctrl.c
> @@ -48,11 +48,6 @@ struct pcie_bwctrl_data {
>  /* Prevent port removal during Link Speed changes. */
>  static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
>  
> -static bool pcie_valid_speed(enum pci_bus_speed speed)
> -{
> -	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
> -}
> -
>  static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
>  {
>  	static const u8 speed_conv[] = {
> -- 
> 2.34.1
> 

Re: [PATCH v7 1/3] PCI: Add public pcie_valid_speed() for shared validation

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 2411 bytes --]

On Thu, 11 Jun 2026, Bjorn Helgaas wrote:

> On Tue, Apr 07, 2026 at 09:04:48PM +0800, Hans Zhang wrote:
> > Extract the PCIe speed validation logic from bwctrl.c's static
> > pcie_valid_speed() into a public static inline function in pci.h.
> > 
> > This allows consistent speed range checks (2.5GT/s to 64.0GT/s) across
> > multiple drivers and functions, avoiding duplicate code and ensuring
> > validation consistency as per PCIe specifications.
> > 
> > Signed-off-by: Hans Zhang <18255117159@163.com>
> > Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> 
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> 
> Any objection, Ilpo?
> 
> It looks like 1/3 and 2/3 are pure moves, and the interesting part is
> the use in dwc, which I'd like to be reviewed and applied by Mani.

I went through the patches, no "objections" in the main sense of the word.

For PATCH 1 and 2,

Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

I'll write some of my thoughts to the patch 3.

--
 i.

> > ---
> >  drivers/pci/pci.h         | 5 +++++
> >  drivers/pci/pcie/bwctrl.c | 5 -----
> >  2 files changed, 5 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index 4a14f88e543a..f0a082bfd6f1 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -606,6 +606,11 @@ void pci_bus_put(struct pci_bus *bus);
> >  	 (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
> >  	 0)
> >  
> > +static inline bool pcie_valid_speed(enum pci_bus_speed speed)
> > +{
> > +	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
> > +}
> > +
> >  static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
> >  {
> >  	switch (speed) {
> > diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
> > index c4c8d260bf96..ea82e326f164 100644
> > --- a/drivers/pci/pcie/bwctrl.c
> > +++ b/drivers/pci/pcie/bwctrl.c
> > @@ -48,11 +48,6 @@ struct pcie_bwctrl_data {
> >  /* Prevent port removal during Link Speed changes. */
> >  static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
> >  
> > -static bool pcie_valid_speed(enum pci_bus_speed speed)
> > -{
> > -	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
> > -}
> > -
> >  static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
> >  {
> >  	static const u8 speed_conv[] = {
> > -- 
> > 2.34.1
> > 
> 

Re: [PATCH v7 1/3] PCI: Add public pcie_valid_speed() for shared validation

[Hans Zhang]

On 6/12/26 01:23, Bjorn Helgaas wrote:
> On Tue, Apr 07, 2026 at 09:04:48PM +0800, Hans Zhang wrote:
>> Extract the PCIe speed validation logic from bwctrl.c's static
>> pcie_valid_speed() into a public static inline function in pci.h.
>>
>> This allows consistent speed range checks (2.5GT/s to 64.0GT/s) across
>> multiple drivers and functions, avoiding duplicate code and ensuring
>> validation consistency as per PCIe specifications.
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> 
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> 
> Any objection, Ilpo?
> 
> It looks like 1/3 and 2/3 are pure moves, and the interesting part is
> the use in dwc, which I'd like to be reviewed and applied by Mani.

Hi Mani,

Gentle ping on this series. Please apply it when you have time. Thank 
you very much!

Best regards,
Hans

> 
>> ---
>>   drivers/pci/pci.h         | 5 +++++
>>   drivers/pci/pcie/bwctrl.c | 5 -----
>>   2 files changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
>> index 4a14f88e543a..f0a082bfd6f1 100644
>> --- a/drivers/pci/pci.h
>> +++ b/drivers/pci/pci.h
>> @@ -606,6 +606,11 @@ void pci_bus_put(struct pci_bus *bus);
>>   	 (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
>>   	 0)
>>   
>> +static inline bool pcie_valid_speed(enum pci_bus_speed speed)
>> +{
>> +	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
>> +}
>> +
>>   static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
>>   {
>>   	switch (speed) {
>> diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
>> index c4c8d260bf96..ea82e326f164 100644
>> --- a/drivers/pci/pcie/bwctrl.c
>> +++ b/drivers/pci/pcie/bwctrl.c
>> @@ -48,11 +48,6 @@ struct pcie_bwctrl_data {
>>   /* Prevent port removal during Link Speed changes. */
>>   static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
>>   
>> -static bool pcie_valid_speed(enum pci_bus_speed speed)
>> -{
>> -	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
>> -}
>> -
>>   static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
>>   {
>>   	static const u8 speed_conv[] = {
>> -- 
>> 2.34.1
>>

Re: [PATCH v7 1/3] PCI: Add public pcie_valid_speed() for shared validation

[Hans Zhang]

On 6/15/26 23:17, Hans Zhang wrote:
> 
> 
> On 6/12/26 01:23, Bjorn Helgaas wrote:
>> On Tue, Apr 07, 2026 at 09:04:48PM +0800, Hans Zhang wrote:
>>> Extract the PCIe speed validation logic from bwctrl.c's static
>>> pcie_valid_speed() into a public static inline function in pci.h.
>>>
>>> This allows consistent speed range checks (2.5GT/s to 64.0GT/s) across
>>> multiple drivers and functions, avoiding duplicate code and ensuring
>>> validation consistency as per PCIe specifications.
>>>
>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
>>
>> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>>
>> Any objection, Ilpo?
>>
>> It looks like 1/3 and 2/3 are pure moves, and the interesting part is
>> the use in dwc, which I'd like to be reviewed and applied by Mani.
> 
> Hi Mani,
> 
> Gentle ping on this series. Please apply it when you have time. Thank 
> you very much!

Hello Mani,

May I check if there is still window to merge it into v7.2-RC1?

Best regards,
Hans


> 
> Best regards,
> Hans
> 
>>
>>> ---
>>>   drivers/pci/pci.h         | 5 +++++
>>>   drivers/pci/pcie/bwctrl.c | 5 -----
>>>   2 files changed, 5 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
>>> index 4a14f88e543a..f0a082bfd6f1 100644
>>> --- a/drivers/pci/pci.h
>>> +++ b/drivers/pci/pci.h
>>> @@ -606,6 +606,11 @@ void pci_bus_put(struct pci_bus *bus);
>>>        (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
>>>        0)
>>> +static inline bool pcie_valid_speed(enum pci_bus_speed speed)
>>> +{
>>> +    return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
>>> +}
>>> +
>>>   static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
>>>   {
>>>       switch (speed) {
>>> diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
>>> index c4c8d260bf96..ea82e326f164 100644
>>> --- a/drivers/pci/pcie/bwctrl.c
>>> +++ b/drivers/pci/pcie/bwctrl.c
>>> @@ -48,11 +48,6 @@ struct pcie_bwctrl_data {
>>>   /* Prevent port removal during Link Speed changes. */
>>>   static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
>>> -static bool pcie_valid_speed(enum pci_bus_speed speed)
>>> -{
>>> -    return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
>>> -}
>>> -
>>>   static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
>>>   {
>>>       static const u8 speed_conv[] = {
>>> -- 
>>> 2.34.1
>>>
> 

Re: [PATCH v7 1/3] PCI: Add public pcie_valid_speed() for shared validation

[Bjorn Helgaas]

On Fri, Jun 19, 2026 at 11:33:11PM +0800, Hans Zhang wrote:
> On 6/15/26 23:17, Hans Zhang wrote:
> > On 6/12/26 01:23, Bjorn Helgaas wrote:
> > > On Tue, Apr 07, 2026 at 09:04:48PM +0800, Hans Zhang wrote:
> > > > Extract the PCIe speed validation logic from bwctrl.c's static
> > > > pcie_valid_speed() into a public static inline function in pci.h.
> > > > 
> > > > This allows consistent speed range checks (2.5GT/s to 64.0GT/s) across
> > > > multiple drivers and functions, avoiding duplicate code and ensuring
> > > > validation consistency as per PCIe specifications.
> > > > 
> > > > Signed-off-by: Hans Zhang <18255117159@163.com>
> > > > Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> > > 
> > > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> > > 
> > > Any objection, Ilpo?
> > > 
> > > It looks like 1/3 and 2/3 are pure moves, and the interesting part is
> > > the use in dwc, which I'd like to be reviewed and applied by Mani.
> > 
> > Hi Mani,
> > 
> > Gentle ping on this series. Please apply it when you have time. Thank
> > you very much!
> 
> Hello Mani,
> 
> May I check if there is still window to merge it into v7.2-RC1?

There is not.  Unless there's some catastrophe the bits in pci/next
are what will be in v7.2-rc1 (I will update some merge commit logs,
but "git diff 40e92a5476e7 pci/next" should be empty).

> > > > ---
> > > >   drivers/pci/pci.h         | 5 +++++
> > > >   drivers/pci/pcie/bwctrl.c | 5 -----
> > > >   2 files changed, 5 insertions(+), 5 deletions(-)
> > > > 
> > > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > > > index 4a14f88e543a..f0a082bfd6f1 100644
> > > > --- a/drivers/pci/pci.h
> > > > +++ b/drivers/pci/pci.h
> > > > @@ -606,6 +606,11 @@ void pci_bus_put(struct pci_bus *bus);
> > > >        (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
> > > >        0)
> > > > +static inline bool pcie_valid_speed(enum pci_bus_speed speed)
> > > > +{
> > > > +    return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
> > > > +}
> > > > +
> > > >   static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
> > > >   {
> > > >       switch (speed) {
> > > > diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
> > > > index c4c8d260bf96..ea82e326f164 100644
> > > > --- a/drivers/pci/pcie/bwctrl.c
> > > > +++ b/drivers/pci/pcie/bwctrl.c
> > > > @@ -48,11 +48,6 @@ struct pcie_bwctrl_data {
> > > >   /* Prevent port removal during Link Speed changes. */
> > > >   static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
> > > > -static bool pcie_valid_speed(enum pci_bus_speed speed)
> > > > -{
> > > > -    return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
> > > > -}
> > > > -
> > > >   static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
> > > >   {
> > > >       static const u8 speed_conv[] = {
> > > > -- 
> > > > 2.34.1
> > > > 
> > 
> 

Re: [PATCH v7 1/3] PCI: Add public pcie_valid_speed() for shared validation

[Hans Zhang]

On 6/23/26 01:16, Bjorn Helgaas wrote:
> On Fri, Jun 19, 2026 at 11:33:11PM +0800, Hans Zhang wrote:
>> On 6/15/26 23:17, Hans Zhang wrote:
>>> On 6/12/26 01:23, Bjorn Helgaas wrote:
>>>> On Tue, Apr 07, 2026 at 09:04:48PM +0800, Hans Zhang wrote:
>>>>> Extract the PCIe speed validation logic from bwctrl.c's static
>>>>> pcie_valid_speed() into a public static inline function in pci.h.
>>>>>
>>>>> This allows consistent speed range checks (2.5GT/s to 64.0GT/s) across
>>>>> multiple drivers and functions, avoiding duplicate code and ensuring
>>>>> validation consistency as per PCIe specifications.
>>>>>
>>>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>>>> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
>>>>
>>>> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
>>>>
>>>> Any objection, Ilpo?
>>>>
>>>> It looks like 1/3 and 2/3 are pure moves, and the interesting part is
>>>> the use in dwc, which I'd like to be reviewed and applied by Mani.
>>>
>>> Hi Mani,
>>>
>>> Gentle ping on this series. Please apply it when you have time. Thank
>>> you very much!
>>
>> Hello Mani,
>>
>> May I check if there is still window to merge it into v7.2-RC1?
> 
> There is not.  Unless there's some catastrophe the bits in pci/next
> are what will be in v7.2-rc1 (I will update some merge commit logs,
> but "git diff 40e92a5476e7 pci/next" should be empty).

Hello Mani,

Please apply this series when you have time. Thank you very much!

Best regards,
Hans

> 
>>>>> ---
>>>>>    drivers/pci/pci.h         | 5 +++++
>>>>>    drivers/pci/pcie/bwctrl.c | 5 -----
>>>>>    2 files changed, 5 insertions(+), 5 deletions(-)
>>>>>
>>>>> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
>>>>> index 4a14f88e543a..f0a082bfd6f1 100644
>>>>> --- a/drivers/pci/pci.h
>>>>> +++ b/drivers/pci/pci.h
>>>>> @@ -606,6 +606,11 @@ void pci_bus_put(struct pci_bus *bus);
>>>>>         (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
>>>>>         0)
>>>>> +static inline bool pcie_valid_speed(enum pci_bus_speed speed)
>>>>> +{
>>>>> +    return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
>>>>> +}
>>>>> +
>>>>>    static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
>>>>>    {
>>>>>        switch (speed) {
>>>>> diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
>>>>> index c4c8d260bf96..ea82e326f164 100644
>>>>> --- a/drivers/pci/pcie/bwctrl.c
>>>>> +++ b/drivers/pci/pcie/bwctrl.c
>>>>> @@ -48,11 +48,6 @@ struct pcie_bwctrl_data {
>>>>>    /* Prevent port removal during Link Speed changes. */
>>>>>    static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
>>>>> -static bool pcie_valid_speed(enum pci_bus_speed speed)
>>>>> -{
>>>>> -    return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
>>>>> -}
>>>>> -
>>>>>    static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
>>>>>    {
>>>>>        static const u8 speed_conv[] = {
>>>>> -- 
>>>>> 2.34.1
>>>>>
>>>
>>

[PATCH v7 2/3] PCI: Move pci_bus_speed2lnkctl2() to public header

[Hans Zhang]

Move the static array-based pci_bus_speed2lnkctl2() function from
bwctrl.c to pci.h as a public inline function.

This provides efficient O(1) speed-to-LNKCTL2 value conversion using
static array lookup, maintaining optimal performance while enabling
code reuse by other PCIe drivers.

Signed-off-by: Hans Zhang <18255117159@163.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
---
 drivers/pci/pci.h         | 18 ++++++++++++++++++
 drivers/pci/pcie/bwctrl.c | 17 -----------------
 2 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index f0a082bfd6f1..e0c2630e93f2 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -2,6 +2,7 @@
 #ifndef DRIVERS_PCI_H
 #define DRIVERS_PCI_H
 
+#include <asm/bug.h>
 #include <linux/align.h>
 #include <linux/bitfield.h>
 #include <linux/pci.h>
@@ -611,6 +612,23 @@ static inline bool pcie_valid_speed(enum pci_bus_speed speed)
 	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
 }
 
+static inline u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
+{
+	static const u8 speed_conv[] = {
+		[PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT,
+		[PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT,
+		[PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT,
+		[PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
+		[PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
+		[PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
+	};
+
+	if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
+		return 0;
+
+	return speed_conv[speed];
+}
+
 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
 {
 	switch (speed) {
diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
index ea82e326f164..d48021bfd844 100644
--- a/drivers/pci/pcie/bwctrl.c
+++ b/drivers/pci/pcie/bwctrl.c
@@ -48,23 +48,6 @@ struct pcie_bwctrl_data {
 /* Prevent port removal during Link Speed changes. */
 static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
 
-static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
-{
-	static const u8 speed_conv[] = {
-		[PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT,
-		[PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT,
-		[PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT,
-		[PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
-		[PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
-		[PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
-	};
-
-	if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
-		return 0;
-
-	return speed_conv[speed];
-}
-
 static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
 {
 	return __fls(supported_speeds);
-- 
2.34.1

Re: [PATCH v7 2/3] PCI: Move pci_bus_speed2lnkctl2() to public header

[Bjorn Helgaas]

On Tue, Apr 07, 2026 at 09:04:49PM +0800, Hans Zhang wrote:
> Move the static array-based pci_bus_speed2lnkctl2() function from
> bwctrl.c to pci.h as a public inline function.
> 
> This provides efficient O(1) speed-to-LNKCTL2 value conversion using
> static array lookup, maintaining optimal performance while enabling
> code reuse by other PCIe drivers.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> ---
>  drivers/pci/pci.h         | 18 ++++++++++++++++++
>  drivers/pci/pcie/bwctrl.c | 17 -----------------
>  2 files changed, 18 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index f0a082bfd6f1..e0c2630e93f2 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -2,6 +2,7 @@
>  #ifndef DRIVERS_PCI_H
>  #define DRIVERS_PCI_H
>  
> +#include <asm/bug.h>
>  #include <linux/align.h>
>  #include <linux/bitfield.h>
>  #include <linux/pci.h>
> @@ -611,6 +612,23 @@ static inline bool pcie_valid_speed(enum pci_bus_speed speed)
>  	return (speed >= PCIE_SPEED_2_5GT) && (speed <= PCIE_SPEED_64_0GT);
>  }
>  
> +static inline u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
> +{
> +	static const u8 speed_conv[] = {
> +		[PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT,
> +		[PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT,
> +		[PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT,
> +		[PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
> +		[PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
> +		[PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
> +	};
> +
> +	if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
> +		return 0;
> +
> +	return speed_conv[speed];
> +}
> +
>  static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
>  {
>  	switch (speed) {
> diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c
> index ea82e326f164..d48021bfd844 100644
> --- a/drivers/pci/pcie/bwctrl.c
> +++ b/drivers/pci/pcie/bwctrl.c
> @@ -48,23 +48,6 @@ struct pcie_bwctrl_data {
>  /* Prevent port removal during Link Speed changes. */
>  static DECLARE_RWSEM(pcie_bwctrl_setspeed_rwsem);
>  
> -static u16 pci_bus_speed2lnkctl2(enum pci_bus_speed speed)
> -{
> -	static const u8 speed_conv[] = {
> -		[PCIE_SPEED_2_5GT] = PCI_EXP_LNKCTL2_TLS_2_5GT,
> -		[PCIE_SPEED_5_0GT] = PCI_EXP_LNKCTL2_TLS_5_0GT,
> -		[PCIE_SPEED_8_0GT] = PCI_EXP_LNKCTL2_TLS_8_0GT,
> -		[PCIE_SPEED_16_0GT] = PCI_EXP_LNKCTL2_TLS_16_0GT,
> -		[PCIE_SPEED_32_0GT] = PCI_EXP_LNKCTL2_TLS_32_0GT,
> -		[PCIE_SPEED_64_0GT] = PCI_EXP_LNKCTL2_TLS_64_0GT,
> -	};
> -
> -	if (WARN_ON_ONCE(!pcie_valid_speed(speed)))
> -		return 0;
> -
> -	return speed_conv[speed];
> -}
> -
>  static inline u16 pcie_supported_speeds2target_speed(u8 supported_speeds)
>  {
>  	return __fls(supported_speeds);
> -- 
> 2.34.1
> 

[PATCH v7 3/3] PCI: dwc: Use common speed conversion function

[Hans Zhang]

Replace the private switch-based speed conversion in
dw_pcie_link_set_max_speed() with the public pci_bus_speed2lnkctl2()
function.

This eliminates duplicate conversion logic and ensures consistency with
other PCIe drivers, while handling invalid speeds by falling back to
hardware capabilities.

Signed-off-by: Hans Zhang <18255117159@163.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------
 1 file changed, 9 insertions(+), 19 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 06792ba92aa7..10895f6a8e6e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -843,8 +843,10 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
 
 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
 {
-	u32 cap, ctrl2, link_speed;
+	u32 cap, ctrl2;
+	enum pci_bus_speed link_speed;
 	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+	u16 ctrl2_speed;
 
 	cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
 
@@ -861,30 +863,18 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
 	ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
 	ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
 
-	switch (pcie_get_link_speed(pci->max_link_speed)) {
-	case PCIE_SPEED_2_5GT:
-		link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
-		break;
-	case PCIE_SPEED_5_0GT:
-		link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
-		break;
-	case PCIE_SPEED_8_0GT:
-		link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
-		break;
-	case PCIE_SPEED_16_0GT:
-		link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
-		break;
-	default:
+	link_speed = pcie_get_link_speed(pci->max_link_speed);
+	ctrl2_speed = pci_bus_speed2lnkctl2(link_speed);
+	if (ctrl2_speed == 0) {
 		/* Use hardware capability */
-		link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
+		ctrl2_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
 		ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
-		break;
 	}
 
-	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
+	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | ctrl2_speed);
 
 	cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
-	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
+	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | ctrl2_speed);
 
 }
 
-- 
2.34.1

Re: [PATCH v7 3/3] PCI: dwc: Use common speed conversion function

[Ilpo Järvinen]

On Tue, 7 Apr 2026, Hans Zhang wrote:

> Replace the private switch-based speed conversion in
> dw_pcie_link_set_max_speed() with the public pci_bus_speed2lnkctl2()
> function.
> 
> This eliminates duplicate conversion logic and ensures consistency with
> other PCIe drivers, while handling invalid speeds by falling back to
> hardware capabilities.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------
>  1 file changed, 9 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 06792ba92aa7..10895f6a8e6e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -843,8 +843,10 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
>  
>  static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
>  {
> -	u32 cap, ctrl2, link_speed;
> +	u32 cap, ctrl2;
> +	enum pci_bus_speed link_speed;
>  	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +	u16 ctrl2_speed;
>  
>  	cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
>  
> @@ -861,30 +863,18 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
>  	ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
>  	ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;

Not directly related to this patch but I wonder why this function gets the 
speed from LNKCTL2 instead of taking it from LNKCAP2_SLS.

>  
> -	switch (pcie_get_link_speed(pci->max_link_speed)) {
> -	case PCIE_SPEED_2_5GT:
> -		link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
> -		break;
> -	case PCIE_SPEED_5_0GT:
> -		link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
> -		break;
> -	case PCIE_SPEED_8_0GT:
> -		link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
> -		break;
> -	case PCIE_SPEED_16_0GT:
> -		link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
> -		break;
> -	default:
> +	link_speed = pcie_get_link_speed(pci->max_link_speed);
> +	ctrl2_speed = pci_bus_speed2lnkctl2(link_speed);
> +	if (ctrl2_speed == 0) {
>  		/* Use hardware capability */
> -		link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
> +		ctrl2_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
>  		ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
> -		break;
>  	}

I again lament a bit that pcie_capability_read_*() cannot be used early in 
the controller drivers, which might allow using e.g. 
pcie_get_supported_speeds() here (depending on whether the small 
differences this function has compared it are really meaningful or not). 

But this is not really a problem this series is trying to address so as 
stated in my comment to the other patch, no objection to this change.

> -	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
> +	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | ctrl2_speed);
>  
>  	cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
> -	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
> +	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | ctrl2_speed);
>  
>  }
>  
> 

-- 
 i.

Re: [PATCH v7 3/3] PCI: dwc: Use common speed conversion function

[Hans Zhang]

On 6/12/26 01:55, Ilpo Järvinen wrote:
> On Tue, 7 Apr 2026, Hans Zhang wrote:
> 
>> Replace the private switch-based speed conversion in
>> dw_pcie_link_set_max_speed() with the public pci_bus_speed2lnkctl2()
>> function.
>>
>> This eliminates duplicate conversion logic and ensures consistency with
>> other PCIe drivers, while handling invalid speeds by falling back to
>> hardware capabilities.
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
>> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
>> ---
>>   drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------
>>   1 file changed, 9 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
>> index 06792ba92aa7..10895f6a8e6e 100644
>> --- a/drivers/pci/controller/dwc/pcie-designware.c
>> +++ b/drivers/pci/controller/dwc/pcie-designware.c
>> @@ -843,8 +843,10 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
>>   
>>   static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
>>   {
>> -	u32 cap, ctrl2, link_speed;
>> +	u32 cap, ctrl2;
>> +	enum pci_bus_speed link_speed;
>>   	u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
>> +	u16 ctrl2_speed;
>>   
>>   	cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
>>   
>> @@ -861,30 +863,18 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
>>   	ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
>>   	ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
> 
> Not directly related to this patch but I wonder why this function gets the
> speed from LNKCTL2 instead of taking it from LNKCAP2_SLS.

Hi Ilpo,

Thank you for your review and the helpful observations.

Regarding the use of LNKCTL2 vs LNKCAP2_SLS – I will investigate the 
current design choice in dw_pcie_link_set_max_speed() and see if there 
is room for improvement in a future patch.

Since you have no objection to this change, I will keep this patch
as is for now. I'll put the points you raised on my TODO list for
potential follow-up cleanups.

Thanks again for your time.

Best regards,
Hans

> 
>>   
>> -	switch (pcie_get_link_speed(pci->max_link_speed)) {
>> -	case PCIE_SPEED_2_5GT:
>> -		link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
>> -		break;
>> -	case PCIE_SPEED_5_0GT:
>> -		link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
>> -		break;
>> -	case PCIE_SPEED_8_0GT:
>> -		link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
>> -		break;
>> -	case PCIE_SPEED_16_0GT:
>> -		link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
>> -		break;
>> -	default:
>> +	link_speed = pcie_get_link_speed(pci->max_link_speed);
>> +	ctrl2_speed = pci_bus_speed2lnkctl2(link_speed);
>> +	if (ctrl2_speed == 0) {
>>   		/* Use hardware capability */
>> -		link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
>> +		ctrl2_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
>>   		ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
>> -		break;
>>   	}
> 
> I again lament a bit that pcie_capability_read_*() cannot be used early in
> the controller drivers, which might allow using e.g.
> pcie_get_supported_speeds() here (depending on whether the small
> differences this function has compared it are really meaningful or not).
> 
> But this is not really a problem this series is trying to address so as
> stated in my comment to the other patch, no objection to this change.
> 
>> -	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
>> +	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | ctrl2_speed);
>>   
>>   	cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
>> -	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
>> +	dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | ctrl2_speed);
>>   
>>   }
>>   
>>
> 

Re: [PATCH v7 0/3] PCI: Refactor PCIe speed validation and conversion functions

[Hans Zhang]

Hi Bjorn,

May I ask if there's any chance for this series to be included in v7.1?

Best regards,
Hans

On 4/7/26 21:04, Hans Zhang wrote:
> This series refactors PCIe speed validation and conversion logic to
> shared functions in the public header, eliminating code duplication
> and ensuring consistency across drivers.
> 
> ---
> Changes for v7:
> - patch 0002 add #include <asm/bug.h> (Ilpo)
> - s/u32 link_speed/enum pci_bus_speed link_speed/ (Ilpo)
> - The return value of pci_bus_speed2lnkctl2 uses the variable ctrl2_speed
>    to avoid the abuse of variable types. (Ilpo)
> 
> Changes for v6:
> https://patchwork.kernel.org/project/linux-pci/patch/20260406105613.1228673-1-18255117159@163.com/
> 
> - missing one line of code:
>    link_speed = pcie_get_link_speed(pci->max_link_speed);
> 
> Changes for v5:
> https://patchwork.kernel.org/project/linux-pci/patch/20260406104708.1218648-1-18255117159@163.com/
> 
> - Rebase to v7.0-rc1. (pci/next tree)
> 
> Changes for v4:
> https://patchwork.kernel.org/project/linux-pci/patch/20251102143206.111347-1-18255117159@163.com/
> 
> - Maintain O(1) array-based lookup for speed conversion (addressing
>    performance concerns from v3 feedback)
> - Move pcie_valid_speed() and pci_bus_speed2lnkctl2() to pci.h
> - Update dwc driver to use the shared functions
> - Rebase to v6.18-rc3.
> 
> This addresses the feedback from Lukas Wunner and Manivannan Sadhasivam
> on the v3 submission, ensuring no runtime performance regression while
> achieving code reuse.
> 
> Changes for v3:
> https://patchwork.kernel.org/project/linux-pci/patch/20250816154633.338653-1-18255117159@163.com/
> 
> - Rebase to v6.17-rc1.
> - Gentle ping.
> 
> Changes for v2:
> - s/PCIE_SPEED2LNKCTL2_TLS_ENC/PCIE_SPEED2LNKCTL2_TLS
> - The patch commit message were modified.
> ---
> 
> Hans Zhang (3):
>    PCI: Add public pcie_valid_speed() for shared validation
>    PCI: Move pci_bus_speed2lnkctl2() to public header
>    PCI: dwc: Use common speed conversion function
> 
>   drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------
>   drivers/pci/pci.h                            | 23 ++++++++++++++++
>   drivers/pci/pcie/bwctrl.c                    | 22 ---------------
>   3 files changed, 32 insertions(+), 41 deletions(-)
> 
> 
> base-commit: 525e91d84dc085492b36d4b87abb7c1cc93fcb44

Re: [PATCH v7 0/3] PCI: Refactor PCIe speed validation and conversion functions

[Hans Zhang]

Hi Bjorn,

Gentle ping.

Best regards,
Hans

On 4/7/26 21:04, Hans Zhang wrote:
> This series refactors PCIe speed validation and conversion logic to
> shared functions in the public header, eliminating code duplication
> and ensuring consistency across drivers.
> 
> ---
> Changes for v7:
> - patch 0002 add #include <asm/bug.h> (Ilpo)
> - s/u32 link_speed/enum pci_bus_speed link_speed/ (Ilpo)
> - The return value of pci_bus_speed2lnkctl2 uses the variable ctrl2_speed
>    to avoid the abuse of variable types. (Ilpo)
> 
> Changes for v6:
> https://patchwork.kernel.org/project/linux-pci/patch/20260406105613.1228673-1-18255117159@163.com/
> 
> - missing one line of code:
>    link_speed = pcie_get_link_speed(pci->max_link_speed);
> 
> Changes for v5:
> https://patchwork.kernel.org/project/linux-pci/patch/20260406104708.1218648-1-18255117159@163.com/
> 
> - Rebase to v7.0-rc1. (pci/next tree)
> 
> Changes for v4:
> https://patchwork.kernel.org/project/linux-pci/patch/20251102143206.111347-1-18255117159@163.com/
> 
> - Maintain O(1) array-based lookup for speed conversion (addressing
>    performance concerns from v3 feedback)
> - Move pcie_valid_speed() and pci_bus_speed2lnkctl2() to pci.h
> - Update dwc driver to use the shared functions
> - Rebase to v6.18-rc3.
> 
> This addresses the feedback from Lukas Wunner and Manivannan Sadhasivam
> on the v3 submission, ensuring no runtime performance regression while
> achieving code reuse.
> 
> Changes for v3:
> https://patchwork.kernel.org/project/linux-pci/patch/20250816154633.338653-1-18255117159@163.com/
> 
> - Rebase to v6.17-rc1.
> - Gentle ping.
> 
> Changes for v2:
> - s/PCIE_SPEED2LNKCTL2_TLS_ENC/PCIE_SPEED2LNKCTL2_TLS
> - The patch commit message were modified.
> ---
> 
> Hans Zhang (3):
>    PCI: Add public pcie_valid_speed() for shared validation
>    PCI: Move pci_bus_speed2lnkctl2() to public header
>    PCI: dwc: Use common speed conversion function
> 
>   drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------
>   drivers/pci/pci.h                            | 23 ++++++++++++++++
>   drivers/pci/pcie/bwctrl.c                    | 22 ---------------
>   3 files changed, 32 insertions(+), 41 deletions(-)
> 
> 
> base-commit: 525e91d84dc085492b36d4b87abb7c1cc93fcb44

Re: [PATCH v7 0/3] PCI: Refactor PCIe speed validation and conversion functions

[Hans Zhang]

Hello Bjorn,

Gentle ping. Please take a look at this series.

Best regards,
Hans

On 4/7/26 21:04, Hans Zhang wrote:
> This series refactors PCIe speed validation and conversion logic to
> shared functions in the public header, eliminating code duplication
> and ensuring consistency across drivers.
> 
> ---
> Changes for v7:
> - patch 0002 add #include <asm/bug.h> (Ilpo)
> - s/u32 link_speed/enum pci_bus_speed link_speed/ (Ilpo)
> - The return value of pci_bus_speed2lnkctl2 uses the variable ctrl2_speed
>    to avoid the abuse of variable types. (Ilpo)
> 
> Changes for v6:
> https://patchwork.kernel.org/project/linux-pci/patch/20260406105613.1228673-1-18255117159@163.com/
> 
> - missing one line of code:
>    link_speed = pcie_get_link_speed(pci->max_link_speed);
> 
> Changes for v5:
> https://patchwork.kernel.org/project/linux-pci/patch/20260406104708.1218648-1-18255117159@163.com/
> 
> - Rebase to v7.0-rc1. (pci/next tree)
> 
> Changes for v4:
> https://patchwork.kernel.org/project/linux-pci/patch/20251102143206.111347-1-18255117159@163.com/
> 
> - Maintain O(1) array-based lookup for speed conversion (addressing
>    performance concerns from v3 feedback)
> - Move pcie_valid_speed() and pci_bus_speed2lnkctl2() to pci.h
> - Update dwc driver to use the shared functions
> - Rebase to v6.18-rc3.
> 
> This addresses the feedback from Lukas Wunner and Manivannan Sadhasivam
> on the v3 submission, ensuring no runtime performance regression while
> achieving code reuse.
> 
> Changes for v3:
> https://patchwork.kernel.org/project/linux-pci/patch/20250816154633.338653-1-18255117159@163.com/
> 
> - Rebase to v6.17-rc1.
> - Gentle ping.
> 
> Changes for v2:
> - s/PCIE_SPEED2LNKCTL2_TLS_ENC/PCIE_SPEED2LNKCTL2_TLS
> - The patch commit message were modified.
> ---
> 
> Hans Zhang (3):
>    PCI: Add public pcie_valid_speed() for shared validation
>    PCI: Move pci_bus_speed2lnkctl2() to public header
>    PCI: dwc: Use common speed conversion function
> 
>   drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------
>   drivers/pci/pci.h                            | 23 ++++++++++++++++
>   drivers/pci/pcie/bwctrl.c                    | 22 ---------------
>   3 files changed, 32 insertions(+), 41 deletions(-)
> 
> 
> base-commit: 525e91d84dc085492b36d4b87abb7c1cc93fcb44

Re: [PATCH v7 0/3] PCI: Refactor PCIe speed validation and conversion functions

[Hans Zhang]

Hello Mani,

Gentle ping on this series. Bjorn has asked you to review and apply this 
series.

https://lore.kernel.org/linux-pci/20260611172301.GA490724@bhelgaas/

Bjorn, Ilpo, and you have added the "Acked-by" and "Reviewed-by" labels. 
I'm not sure if this allows us to proceed to v7.3?

Best regards,
Hans

On 4/7/26 21:04, Hans Zhang wrote:
> This series refactors PCIe speed validation and conversion logic to
> shared functions in the public header, eliminating code duplication
> and ensuring consistency across drivers.
> 
> ---
> Changes for v7:
> - patch 0002 add #include <asm/bug.h> (Ilpo)
> - s/u32 link_speed/enum pci_bus_speed link_speed/ (Ilpo)
> - The return value of pci_bus_speed2lnkctl2 uses the variable ctrl2_speed
>    to avoid the abuse of variable types. (Ilpo)
> 
> Changes for v6:
> https://patchwork.kernel.org/project/linux-pci/patch/20260406105613.1228673-1-18255117159@163.com/
> 
> - missing one line of code:
>    link_speed = pcie_get_link_speed(pci->max_link_speed);
> 
> Changes for v5:
> https://patchwork.kernel.org/project/linux-pci/patch/20260406104708.1218648-1-18255117159@163.com/
> 
> - Rebase to v7.0-rc1. (pci/next tree)
> 
> Changes for v4:
> https://patchwork.kernel.org/project/linux-pci/patch/20251102143206.111347-1-18255117159@163.com/
> 
> - Maintain O(1) array-based lookup for speed conversion (addressing
>    performance concerns from v3 feedback)
> - Move pcie_valid_speed() and pci_bus_speed2lnkctl2() to pci.h
> - Update dwc driver to use the shared functions
> - Rebase to v6.18-rc3.
> 
> This addresses the feedback from Lukas Wunner and Manivannan Sadhasivam
> on the v3 submission, ensuring no runtime performance regression while
> achieving code reuse.
> 
> Changes for v3:
> https://patchwork.kernel.org/project/linux-pci/patch/20250816154633.338653-1-18255117159@163.com/
> 
> - Rebase to v6.17-rc1.
> - Gentle ping.
> 
> Changes for v2:
> - s/PCIE_SPEED2LNKCTL2_TLS_ENC/PCIE_SPEED2LNKCTL2_TLS
> - The patch commit message were modified.
> ---
> 
> Hans Zhang (3):
>    PCI: Add public pcie_valid_speed() for shared validation
>    PCI: Move pci_bus_speed2lnkctl2() to public header
>    PCI: dwc: Use common speed conversion function
> 
>   drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------
>   drivers/pci/pci.h                            | 23 ++++++++++++++++
>   drivers/pci/pcie/bwctrl.c                    | 22 ---------------
>   3 files changed, 32 insertions(+), 41 deletions(-)
> 
> 
> base-commit: 525e91d84dc085492b36d4b87abb7c1cc93fcb44

Re: [PATCH v7 0/3] PCI: Refactor PCIe speed validation and conversion functions

[Manivannan Sadhasivam]

On Tue, 07 Apr 2026 21:04:47 +0800, Hans Zhang wrote:
> This series refactors PCIe speed validation and conversion logic to
> shared functions in the public header, eliminating code duplication
> and ensuring consistency across drivers.

Applied, thanks!

[1/3] PCI: Add public pcie_valid_speed() for shared validation
      commit: e1c1eb1d8912bd209845f1e7fc99925412fc5af8
[2/3] PCI: Move pci_bus_speed2lnkctl2() to public header
      commit: a03c77abaa802433210f193617000a3c1edd20be
[3/3] PCI: dwc: Use common speed conversion function
      commit: 6fc5fcd8ec1bdba3123b8a662410cf70bffc40f0

Best regards,
-- 
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