From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: "Neil Armstrong" <neil.armstrong@linaro.org>,
"Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>
Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: qcom: Advertise hotplug with no command completion support
Date: Fri, 16 Oct 2026 12:47:19 +0200 [thread overview]
Message-ID: <04d85ecc-60fc-4923-9073-6e00eeca5f43@oss.qualcomm.com> (raw)
In-Reply-To: <d709693e-b9ad-4d53-a368-67fbb0cbd601@linaro.org>
On 10/16/26 12:24 PM, Neil Armstrong wrote:
> Hi,
>
> On 3/14/26 02:56, Krishna Chaitanya Chundru wrote:
>> QCOM PCIe controller advertise hotplug capability in hardware but do not
>> support hotplug command completion. As a result, the PCI core registers
>> the pciehp service and issues hotplug commands that never gets completions,
>> leading to repeated timeout warnings and multi-second delays during boot
>> and suspend/resume.
>>
>> Commit a54db86ddc153 ("PCI: qcom: Do not advertise hotplug capability for
>> IPs v2.7.0 and v1.9.0") avoided these timeouts by clearing the Hot-Plug
>> Capability bit entirely, which also disabled all hotplug functionality.
>>
>> Instead of disabling hotplug, mark these controllers as not supporting
>> command completion by setting the No Command Completed Support (NCCS) bit
>> in the Slot Capabilities register. This prevents the PCI hotplug driver
>> from waiting for commands completion while still allowing hotplug-related
>> functionality such as Data Link Layer state change events.
>
> I'm a little late to the party, but marking the RC as Hotplus means the bridge
> is marked as is_pciehp and pci_bridge_d3_possible() returns false.
>
> This means this breaks D3Cold support completely since in __pci_host_common_d3cold_possible()
> we now check all PCI devices, including bridges, and the RC is not set in D3Hot anymore.
>
> The only way to enable D3Cold is to pass pcie_port_pm=force to allow D3 on all
> Hotplug bridges. Which may be wrong on TB bridges.
At a glance, may it be that we should advertise pciehp_is_native=true?
(it's currently only a thing in ACPI world)
Konrad
next prev parent reply other threads:[~2026-10-16 10:47 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-14 1:56 Krishna Chaitanya Chundru
2026-03-15 10:09 ` Manivannan Sadhasivam
2026-03-16 12:22 ` Krishna Chaitanya Chundru
2026-03-19 10:59 ` Konrad Dybcio
2026-03-20 1:40 ` Krishna Chaitanya Chundru
2026-03-21 12:01 ` Manivannan Sadhasivam
2026-03-24 11:27 ` Konrad Dybcio
2026-03-26 18:06 ` Manivannan Sadhasivam
2026-03-26 18:04 ` Manivannan Sadhasivam
2026-10-16 10:24 ` Neil Armstrong
2026-10-16 10:47 ` Konrad Dybcio [this message]
2026-10-16 11:08 ` Krishna Chaitanya Chundru
2026-10-16 12:34 ` Neil Armstrong
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