Re: [PATCH] PCI: qcom: Advertise hotplug with no command completion support

[Neil Armstrong <neil.armstrong@linaro.org>]

Hi,

On 10/16/26 13:08, Krishna Chaitanya Chundru wrote:
> 
> 
> On 10/16/2026 3:54 PM, Neil Armstrong wrote:
>> Hi,
>>
>> On 3/14/26 02:56, Krishna Chaitanya Chundru wrote:
>>> QCOM PCIe controller advertise hotplug capability in hardware but do not
>>> support hotplug command completion. As a result, the PCI core registers
>>> the pciehp service and issues hotplug commands that never gets completions,
>>> leading to repeated timeout warnings and multi-second delays during boot
>>> and suspend/resume.
>>>
>>> Commit a54db86ddc153 ("PCI: qcom: Do not advertise hotplug capability for
>>> IPs v2.7.0 and v1.9.0") avoided these timeouts by clearing the Hot-Plug
>>> Capability bit entirely, which also disabled all hotplug functionality.
>>>
>>> Instead of disabling hotplug, mark these controllers as not supporting
>>> command completion by setting the No Command Completed Support (NCCS) bit
>>> in the Slot Capabilities register. This prevents the PCI hotplug driver
>>> from waiting for commands completion while still allowing hotplug-related
>>> functionality such as Data Link Layer state change events.
>>
>> I'm a little late to the party, but marking the RC as Hotplus means the bridge
>> is marked as is_pciehp and pci_bridge_d3_possible() returns false.
>>
>> This means this breaks D3Cold support completely since in
>> __pci_host_common_d3cold_possible()
>> we now check all PCI devices, including bridges, and the RC is not set in
>> D3Hot anymore.
>>
>> The only way to enable D3Cold is to pass pcie_port_pm=force to allow D3 on all
>> Hotplug bridges. Which may be wrong on TB bridges.
>>
> Hi Neil,
> can you enable hotplug driver and use this patch [1], that should solve the issue.
> 
> [1]
> https://patch.msgid.link/20260729165005.896725-1-manivannan.sadhasivam@oss.qualcomm.com

Thanks this fixes the issue,

Neil

> 
>> Neil
>>
>>>
>>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>>> ---
>>>    drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
>>> b/drivers/pci/controller/dwc/pcie-qcom.c
>>> index
>>> 67a16af69ddc75fca1b123e70715e692a91a9135..a2924610f3625f2456a491473c135840e31bafb9
>>> 100644
>>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>>> @@ -358,7 +358,7 @@ static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
>>>        dw_pcie_dbi_ro_wr_en(pci);
>>>          val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
>>> -    val &= ~PCI_EXP_SLTCAP_HPC;
>>> +    val |= PCI_EXP_SLTCAP_NCCS;
>>>        writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>>>          dw_pcie_dbi_ro_wr_dis(pci);
>>>
>>> ---
>>> base-commit: 0257f64bdac7fdca30fa3cae0df8b9ecbec7733a
>>> change-id: 20260313-hotplug-4c296595b5b8
>>>
>>> Best regards,
>>
>