Re: [PATCH v4 1/6] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding

[Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>]

On 9/24/2026 6:52 PM, Krzysztof Kozlowski wrote:
> On Mon, Sep 21, 2026 at 11:07:09AM +0530, Krishna Chaitanya Chundru wrote:
>> +
>> +  vdda-pll-d-supply: true
>> +
>> +  qcom,link-mode:
>> +    description:
>> +      Reference to the TCSR syscon register containing the PCIe link mode
>> +      selected by firmware. The property consists of the TCSR syscon
>> +      phandle followed by the offset of the TCSR_PCIE_LINK_CONFIG_MODE
>> +      register.
>> +      The register value selects one of these topologies.
>> +        0 (QMP_PCIE_NORD_MODE_X16)         — all ports combined as one x16 PHY
>> +        1 (QMP_PCIE_NORD_MODE_X8_X8)       — port A as x8 and ports B+C+D as x8
>> +        2 (QMP_PCIE_NORD_MODE_X8_X4_X4)    — port A as x8, port B as x4, and ports C+D as x4
>> +        3 (QMP_PCIE_NORD_MODE_X8_X4_X2_X2) — port A as x8, port B as x4, and ports C and D as x2
> Same question as last time. phy-cells tells which mode you are here.
> This is duplicating it and the register value CANNOT choose the
> topology. If it does, then phy-cells should be 0 as topology is defined
> by hardware already, no?
phy-cells does not describe the topology. The PHY argument is only used by the
PCIe controller to identify the PHY instance associated with that controller
(for example, phys = <&pcie_phy 2> selects PHY instance 2).

The qcom,link-mode property serves a different purpose. It provides access to
the firmware-programmed TCSR_PCIE_LINK_CONFIG_MODE register, which describes
the global lane partitioning (x16, x8+x8, x8+x4+x4, x8+x4+x2+x2, etc.).

  - phy-cells identifies which PHY instance a controller is using.
  - qcom,link-mode reports the overall topology selected by firmware.

- Krishna Chaitanya.
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      - items:
>> +          - description: Phandle of the TCSR syscon
>> +          - description: Offset of TCSR_PCIE_LINK_CONFIG_MODE register
> Best regards,
> Krzysztof
>