From: Krzysztof Kozlowski <krzk@kernel.org>
To: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Cc: "Vinod Koul" <vkoul@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Bjorn Andersson" <andersson@kernel.org>,
"Maxime Chevallier" <maxime.chevallier@bootlin.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
shengchao.guo@oss.qualcomm.com, linux-arm-msm@vger.kernel.org,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 1/6] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding
Date: Thu, 24 Sep 2026 15:22:25 +0200 [thread overview]
Message-ID: <20260924-lumpy-robust-fulmar-1bfbe0@quoll> (raw)
In-Reply-To: <20260921-nord-v4-1-ed05c6e09240@oss.qualcomm.com>
On Mon, Sep 21, 2026 at 11:07:09AM +0530, Krishna Chaitanya Chundru wrote:
> +
> + vdda-pll-d-supply: true
> +
> + qcom,link-mode:
> + description:
> + Reference to the TCSR syscon register containing the PCIe link mode
> + selected by firmware. The property consists of the TCSR syscon
> + phandle followed by the offset of the TCSR_PCIE_LINK_CONFIG_MODE
> + register.
> + The register value selects one of these topologies.
> + 0 (QMP_PCIE_NORD_MODE_X16) — all ports combined as one x16 PHY
> + 1 (QMP_PCIE_NORD_MODE_X8_X8) — port A as x8 and ports B+C+D as x8
> + 2 (QMP_PCIE_NORD_MODE_X8_X4_X4) — port A as x8, port B as x4, and ports C+D as x4
> + 3 (QMP_PCIE_NORD_MODE_X8_X4_X2_X2) — port A as x8, port B as x4, and ports C and D as x2
Same question as last time. phy-cells tells which mode you are here.
This is duplicating it and the register value CANNOT choose the
topology. If it does, then phy-cells should be 0 as topology is defined
by hardware already, no?
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: Phandle of the TCSR syscon
> + - description: Offset of TCSR_PCIE_LINK_CONFIG_MODE register
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-09-24 13:22 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 5:37 [PATCH v4 0/6] Add PCIe support for Qualcomm Nord platform Krishna Chaitanya Chundru
2026-09-21 5:37 ` [PATCH v4 1/6] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Krishna Chaitanya Chundru
2026-09-24 13:22 ` Krzysztof Kozlowski [this message]
2026-09-21 5:37 ` [PATCH v4 2/6] dt-bindings: pci: qcom: add Nord PCIe controller compatible Krishna Chaitanya Chundru
2026-09-21 5:37 ` [PATCH v4 3/6] PCI: qcom: Add Nord PCIe controller support Krishna Chaitanya Chundru
2026-09-21 5:37 ` [PATCH v4 4/6] phy: qcom: qmp: Move qphy_setbits/clrbits/checkbits to common header Krishna Chaitanya Chundru
2026-09-21 5:37 ` [PATCH v4 5/6] phy: qcom: qmp-pcie: Refactor common multiphy handling Krishna Chaitanya Chundru
2026-09-22 8:12 ` Shawn Guo
2026-09-21 5:37 ` [PATCH v4 6/6] phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support Krishna Chaitanya Chundru
2026-09-22 8:12 ` Shawn Guo
2026-09-21 6:30 ` [PATCH v4 0/6] Add PCIe support for Qualcomm Nord platform Qiang Yu
2026-09-21 7:37 ` Konrad Dybcio
2026-09-22 9:18 ` Qiang Yu
2026-09-22 8:13 ` Shawn Guo
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