Re: [PATCH v4 0/6] Add PCIe support for Qualcomm Nord platform

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

On Mon, Sep 21, 2026 at 11:07:08AM +0530, Krishna Chaitanya Chundru wrote:
> This series adds PCIe support for the Qualcomm Nord (SA8797P) platform.
> 
> Nord has a single Gen5-capable QMP PCIe PHY block split into four
> independently-clocked and independently-resettable ports (A/B/C/D).
> Firmware selects the active lane topology at boot via a TCSR
> configuration register, and the same PHY block can appear as a single
> x16 port, x8+x8, x8+x4+x4, or x8+x4+x2+x2 depending on that mode. This
> is similar in spirit to the Glymur multi-PHY support already posted,
> except Nord's PHY registers are programmed by Linux rather than by
> firmware, so this series adds the PLL, TXRXZ, PCS and PCS-lane init
> tables along with the power-up/power-down/soft-reset sequencing needed
> to bring each port up.
> 
> The series also documents and wires up the qcom,nord-pcie compatible
> (reusing the existing SA8775P PCIe controller binding), and adds a
> CORE_CLK_CGC_DIS/AUX_PWR_DET workaround required to avoid a timing
> convergence issue in the PCIe power domain.
> 
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> To: Vinod Koul <vkoul@kernel.org>
> To: Neil Armstrong <neil.armstrong@linaro.org>
> To: Rob Herring <robh@kernel.org>
> To: Krzysztof Kozlowski <krzk+dt@kernel.org>
> To: Conor Dooley <conor+dt@kernel.org>
> To: Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> To: Lorenzo Pieralisi <lpieralisi@kernel.org>
> To: Krzysztof Wilczyński <kwilczynski@kernel.org>
> To: Manivannan Sadhasivam <mani@kernel.org>
> To: Bjorn Helgaas <bhelgaas@google.com>
> To: Bjorn Andersson <andersson@kernel.org>
> To: Maxime Chevallier <maxime.chevallier@bootlin.com>
> To: Philipp Zabel <p.zabel@pengutronix.de>
> Cc: shengchao.guo@oss.qualcomm.com
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-phy@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-pci@vger.kernel.org
> Cc: shengchao.guo@oss.qualcomm.com
> 
> ---
> Changes in v4:
> - Couple of nits in dt binding & phy driver (shawn, Mani)
> - Add proper description for link-mode & phy-cells
> - Remove soc node and address cells from example (Mani)
> - change cgc_dis_workaround to disable_cgc (Mani)
> - Split common changes and nord changes (Mani) 
> - Link to v3: https://patch.msgid.link/20260909-nord-v3-0-b0a82721c547@oss.qualcomm.com
> 
> Changes in v3:
> - change the name to quadfurcated phy (Konrad).
> - remove min items and change clocks order (Krzysztof).
> - Factor out the common config and create overlays & try to use common
>   symbols for glymur and nord (Konrad).
> - create  qphy_setbit and qphy_clrbit (Qiang Yu).
> - and in qmp_pcie_exit() apply settings only when nocsr is present (Qiang Yu).
> - Link to v2: https://patch.msgid.link/20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com
> 
> Changes in v2:
> - Fix dtbinding errors (Krzysztof)
> - Link to v1: https://patch.msgid.link/20260825-nord-v1-0-7c02f2b8765a@oss.qualcomm.com
> 
> ---
> Krishna Chaitanya Chundru (6):
>       dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding
>       dt-bindings: pci: qcom: add Nord PCIe controller compatible
>       PCI: qcom: Add Nord PCIe controller support
>       phy: qcom: qmp: Move qphy_setbits/clrbits/checkbits to common header
>       phy: qcom: qmp-pcie: Refactor common multiphy handling
>       phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support

On Nord platform:

Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>