From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Laura Nao <laura.nao@collabora.com>,
mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com,
p.zabel@pengutronix.de, richardcochran@gmail.com
Cc: guangjie.song@mediatek.com, wenst@chromium.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
kernel@collabora.com,
"Nícolas F . R . A . Prado" <nfraprado@collabora.com>
Subject: Re: [PATCH v3 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC
Date: Mon, 4 Aug 2025 16:33:20 +0200 [thread overview]
Message-ID: <061374da-fa6e-4074-9451-1b3722217188@collabora.com> (raw)
In-Reply-To: <29ad5f60-6148-4e9b-8498-83a30a520536@kernel.org>
Il 04/08/25 16:05, Krzysztof Kozlowski ha scritto:
> On 30/07/2025 12:56, Laura Nao wrote:
>>
>> clk_mux->regmap = regmap;
>> + clk_mux->regmap_hwv = regmap_hwv;
>> clk_mux->data = mux;
>> clk_mux->lock = lock;
>> clk_mux->hw.init = &init;
>> @@ -268,6 +329,7 @@ int mtk_clk_register_muxes(struct device *dev,
>> struct clk_hw_onecell_data *clk_data)
>> {
>> struct regmap *regmap;
>> + struct regmap *regmap_hwv;
>> struct clk_hw *hw;
>> int i;
>>
>> @@ -277,6 +339,13 @@ int mtk_clk_register_muxes(struct device *dev,
>> return PTR_ERR(regmap);
>> }
>>
>> + regmap_hwv = mtk_clk_get_hwv_regmap(node);
>> + if (IS_ERR(regmap_hwv)) {
>
> This is either buggy or fragile. mtk_clk_get_hwv_regmap() returns NULL
> or valid pointer... or error? IS_ERR_OR_NULL is not the wait to go.
>
> Choose one - IS_ERR or NULL, preferrably the first, since you must
> handle deferred probe.
>
if regmap_hwv == NULL -> there is no HWV for *this* clock
if regmap_hwv == -ERROR -> there is a HWV for *this* clock, but something
went wrong, we have to return the error.
>> + pr_err("Cannot find hardware voter regmap for %pOF: %pe\n",
>> + node, regmap_hwv);
>> + return PTR_ERR(regmap_hwv);
>> + }
>> +
>> for (i = 0; i < num; i++) {
>> const struct mtk_mux *mux = &muxes[i];
>>
>> @@ -286,7 +355,7 @@ int mtk_clk_register_muxes(struct device *dev,
>> continue;
>> }
>>
>> - hw = mtk_clk_register_mux(dev, mux, regmap, lock);
>> + hw = mtk_clk_register_mux(dev, mux, regmap, regmap_hwv, lock);
>
> So NULL is passed and stored... are you sure this is 100% backwards
> compatible?
>
Yes, it is. This got tested on multiple legacy SoCs in our lab.
>
>
> Best regards,
> Krzysztof
next prev parent reply other threads:[~2025-08-04 14:33 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-30 10:56 [PATCH v3 00/27] Add support for MT8196 clock controllers Laura Nao
2025-07-30 10:56 ` [PATCH v3 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-07-30 10:56 ` [PATCH v3 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-07-30 10:56 ` [PATCH v3 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-07-30 10:56 ` [PATCH v3 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-07-30 10:56 ` [PATCH v3 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-08-04 14:05 ` Krzysztof Kozlowski
2025-08-04 14:33 ` AngeloGioacchino Del Regno [this message]
2025-07-30 10:56 ` [PATCH v3 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-07-30 10:56 ` [PATCH v3 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-07-30 10:56 ` [PATCH v3 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-07-30 10:56 ` [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-01 13:57 ` Rob Herring
2025-08-03 8:17 ` Krzysztof Kozlowski
2025-08-04 8:35 ` Laura Nao
2025-08-04 9:16 ` Krzysztof Kozlowski
2025-08-04 9:27 ` AngeloGioacchino Del Regno
2025-08-04 11:01 ` Krzysztof Kozlowski
2025-08-04 13:27 ` AngeloGioacchino Del Regno
2025-08-04 13:58 ` Krzysztof Kozlowski
2025-08-04 14:15 ` AngeloGioacchino Del Regno
2025-08-04 14:21 ` Krzysztof Kozlowski
2025-08-04 14:25 ` AngeloGioacchino Del Regno
2025-08-04 14:19 ` Krzysztof Kozlowski
2025-08-04 14:31 ` AngeloGioacchino Del Regno
2025-08-04 14:33 ` Krzysztof Kozlowski
2025-08-04 14:35 ` AngeloGioacchino Del Regno
2025-08-03 8:15 ` Krzysztof Kozlowski
2025-07-30 10:56 ` [PATCH v3 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-07-30 10:56 ` [PATCH v3 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-07-30 10:56 ` [PATCH v3 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-07-30 10:56 ` [PATCH v3 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-07-30 10:56 ` [PATCH v3 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-07-30 10:56 ` [PATCH v3 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-07-30 10:56 ` [PATCH v3 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-07-30 10:56 ` [PATCH v3 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-07-30 10:56 ` [PATCH v3 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=061374da-fa6e-4074-9451-1b3722217188@collabora.com \
--to=angelogioacchino.delregno@collabora.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=guangjie.song@mediatek.com \
--cc=kernel@collabora.com \
--cc=krzk+dt@kernel.org \
--cc=krzk@kernel.org \
--cc=laura.nao@collabora.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=mturquette@baylibre.com \
--cc=netdev@vger.kernel.org \
--cc=nfraprado@collabora.com \
--cc=p.zabel@pengutronix.de \
--cc=richardcochran@gmail.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=wenst@chromium.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®