mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Krzysztof Kozlowski <krzk@kernel.org>
To: AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Laura Nao <laura.nao@collabora.com>,
	wenst@chromium.org
Cc: conor+dt@kernel.org, devicetree@vger.kernel.org,
	guangjie.song@mediatek.com, kernel@collabora.com,
	krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com,
	mturquette@baylibre.com, netdev@vger.kernel.org,
	nfraprado@collabora.com, p.zabel@pengutronix.de,
	richardcochran@gmail.com, robh@kernel.org, sboyd@kernel.org
Subject: Re: [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers
Date: Mon, 4 Aug 2025 15:58:50 +0200	[thread overview]
Message-ID: <2555e9fe-3bc0-4f89-9d0b-2f7f946632e7@kernel.org> (raw)
In-Reply-To: <00a12553-b248-4193-8017-22fea07ee196@collabora.com>

On 04/08/2025 15:27, AngeloGioacchino Del Regno wrote:
> 
> We discussed about aggregating votes, yes, in software - this instead is a
> *broken* hardware that does the aggregation internally and does not require
> nor want external drivers to do the aggregation.
> 
>> Maybe it is just the name, so avoid all the confusing "votes" if this is
>> not voting system. If this is a voting system, then don't use custom
>> phandles.
> 
> Being it fundamentally *broken*, this being a voting system is what the hardware
> initially wanted to be - but effectively, since it requires YOU to:
>   - Make sure that power supplies are turned on, if not, turn them on by "touching"
>     HW registers (so, without any assistance from the voter MCU), if any;
>   - Turn on parent clocks manually, if any, before using the "voter mcu" to try
>     to ungate that clock; and
>     - Enable the "FENC" manually, after the mcu says that the clock was ungated.


I understand that "YOU" as Linux driver, when you want to do something
(e.g. toggle) a clock?
If so this looks a lot like power domain, although with some differences.

> 
> in the current state, it is just an hardware managed refcounting system and
> nothing else, because the MCU seems to be unfinished, hence, again, b r o k e n.
> 
> Note that by "manually" I always mean "with direct writes to a clock controller's
> registerS, and without any automation/assistance from the HWV MCU".
> 
> We're using the "hardware-voter" name because this is how MediaTek calls it in the
> datasheets, and no it doesn't really *deserve* that name for what it is exactly in
> MT8196 and MT6991.

Please capture most/all of this in the property description, so it will
be clear that we treat it as some sort of exception and other users of
that property would need similar rationale.

I am asking for this because I do not want this to be re-used for any
other work which would represent something like real voting for
resources. I want it to be clear for whoever looks at it later during
new SoC bringup.

If you send the same code as v4, the same commit msg, just like Laura
did twice in v2 and v3, I will just keep NAKing via mutt macro because
it's a waste of my time.

> 
> And mind you - if using the "interconnect" property for this means that we have to
> add an interconnect driver for it, no, we will not do that, as placing a software

Existing driver(s) can be as well interconnect providers. Same with
power domains.

I do not talk here how you should implement this in the drivers.

> vote that votes clocks in a a voter MCU that does exactly what the interconnect

What is a "software vote"? How did you encode it in DT? Via that phandle?

> driver would do - then requiring virtual/fake clocks - is not a good solution.

We do not add "software votes" in DT as separate properties, because
they are "software". So maybe that's another problem here...

> 
> So, what should we do then?
> 
> Change it to "mediatek,clock-hw-refcounter", and adding a comment to the binding
> saying that this is called "Hardware Voter (HWV)" in the datasheets?
> 
> Or is using the "interconnect" property without any driver in the interconnect API
> actually legit? - Because to me it doesn't look like being legit (and if it is, it
> shouldn't be, as I'm sure that everyone would expect an interconnect API driver
> when encountering an "interconnect" property in DT), and if so, we should just add

Why you would not add any interconnect driver for interconnect API?
Look, the current phandle allows you to poke in some other MMIO space
for the purpose of enabling the clock FOO? So interconnect or power
domains or whatever allows you to have existing or new driver to receive
xlate() and, when requested resources associated with clock FOO.

Instead of the FOO clock driver poking resources, you do
clk_prepare_enable() or pm_domain or icc_enable().



Best regards,
Krzysztof

  reply	other threads:[~2025-08-04 13:58 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-30 10:56 [PATCH v3 00/27] Add support for " Laura Nao
2025-07-30 10:56 ` [PATCH v3 01/27] clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control Laura Nao
2025-07-30 10:56 ` [PATCH v3 02/27] clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC Laura Nao
2025-07-30 10:56 ` [PATCH v3 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd " Laura Nao
2025-07-30 10:56 ` [PATCH v3 04/27] clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap() Laura Nao
2025-07-30 10:56 ` [PATCH v3 05/27] clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENC Laura Nao
2025-08-04 14:05   ` Krzysztof Kozlowski
2025-08-04 14:33     ` AngeloGioacchino Del Regno
2025-07-30 10:56 ` [PATCH v3 06/27] clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct Laura Nao
2025-07-30 10:56 ` [PATCH v3 07/27] clk: mediatek: clk-gate: Add ops for gates with HW voter Laura Nao
2025-07-30 10:56 ` [PATCH v3 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Laura Nao
2025-07-30 10:56 ` [PATCH v3 09/27] dt-bindings: clock: mediatek: Describe MT8196 clock controllers Laura Nao
2025-08-01 13:57   ` Rob Herring
2025-08-03  8:17     ` Krzysztof Kozlowski
2025-08-04  8:35       ` Laura Nao
2025-08-04  9:16         ` Krzysztof Kozlowski
2025-08-04  9:27           ` AngeloGioacchino Del Regno
2025-08-04 11:01             ` Krzysztof Kozlowski
2025-08-04 13:27               ` AngeloGioacchino Del Regno
2025-08-04 13:58                 ` Krzysztof Kozlowski [this message]
2025-08-04 14:15                   ` AngeloGioacchino Del Regno
2025-08-04 14:21                     ` Krzysztof Kozlowski
2025-08-04 14:25                       ` AngeloGioacchino Del Regno
2025-08-04 14:19                   ` Krzysztof Kozlowski
2025-08-04 14:31                     ` AngeloGioacchino Del Regno
2025-08-04 14:33                       ` Krzysztof Kozlowski
2025-08-04 14:35                         ` AngeloGioacchino Del Regno
2025-08-03  8:15   ` Krzysztof Kozlowski
2025-07-30 10:56 ` [PATCH v3 10/27] clk: mediatek: Add MT8196 apmixedsys clock support Laura Nao
2025-07-30 10:56 ` [PATCH v3 11/27] clk: mediatek: Add MT8196 topckgen " Laura Nao
2025-07-30 10:56 ` [PATCH v3 12/27] clk: mediatek: Add MT8196 topckgen2 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 13/27] clk: mediatek: Add MT8196 vlpckgen " Laura Nao
2025-07-30 10:56 ` [PATCH v3 14/27] clk: mediatek: Add MT8196 peripheral " Laura Nao
2025-07-30 10:56 ` [PATCH v3 15/27] clk: mediatek: Add MT8196 ufssys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 16/27] clk: mediatek: Add MT8196 pextpsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 17/27] clk: mediatek: Add MT8196 I2C " Laura Nao
2025-07-30 10:56 ` [PATCH v3 18/27] clk: mediatek: Add MT8196 mcu " Laura Nao
2025-07-30 10:56 ` [PATCH v3 19/27] clk: mediatek: Add MT8196 mdpsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 20/27] clk: mediatek: Add MT8196 mfg " Laura Nao
2025-07-30 10:56 ` [PATCH v3 21/27] clk: mediatek: Add MT8196 disp0 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 22/27] clk: mediatek: Add MT8196 disp1 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 23/27] clk: mediatek: Add MT8196 disp-ao " Laura Nao
2025-07-30 10:56 ` [PATCH v3 24/27] clk: mediatek: Add MT8196 ovl0 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 25/27] clk: mediatek: Add MT8196 ovl1 " Laura Nao
2025-07-30 10:56 ` [PATCH v3 26/27] clk: mediatek: Add MT8196 vdecsys " Laura Nao
2025-07-30 10:56 ` [PATCH v3 27/27] clk: mediatek: Add MT8196 vencsys " Laura Nao

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=2555e9fe-3bc0-4f89-9d0b-2f7f946632e7@kernel.org \
    --to=krzk@kernel.org \
    --cc=angelogioacchino.delregno@collabora.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=guangjie.song@mediatek.com \
    --cc=kernel@collabora.com \
    --cc=krzk+dt@kernel.org \
    --cc=laura.nao@collabora.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=matthias.bgg@gmail.com \
    --cc=mturquette@baylibre.com \
    --cc=netdev@vger.kernel.org \
    --cc=nfraprado@collabora.com \
    --cc=p.zabel@pengutronix.de \
    --cc=richardcochran@gmail.com \
    --cc=robh@kernel.org \
    --cc=sboyd@kernel.org \
    --cc=wenst@chromium.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®