From: Krzysztof Kozlowski <krzk@kernel.org>
To: Larisa Ileana Grigore <larisa.grigore@oss.nxp.com>
Cc: NXP S32 Linux Team <s32@nxp.com>,
Alim Akhtar <alim.akhtar@samsung.com>,
Bart Van Assche <bvanassche@acm.org>,
Bean Huo <beanhuo@micron.com>,
Stanley Jhu <stanleyjhu@google.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"James E.J. Bottomley" <James.Bottomley@hansenpartnership.com>,
"Martin K. Petersen" <mkp@kernel.org>,
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>,
Ajay Neeli <ajay.neeli@amd.com>,
Manivannan Sadhasivam <mani@kernel.org>,
Pedro Sousa <pedrom.sousa@synopsys.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Can Guo <quic_cang@quicinc.com>,
Asutosh Das <quic_asutoshd@quicinc.com>,
imx@lists.linux.dev, linux-scsi@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org, clizzi@redhat.com,
aruizrui@redhat.com, eballetb@redhat.com, echanude@redhat.com,
Frank Li <Frank.Li@nxp.com>
Subject: Re: [PATCH v10 08/11] dt-bindings: ufs: Add NXP S32N79 UFS host controller
Date: Thu, 5 Nov 2026 19:28:14 +0100 [thread overview]
Message-ID: <0820de78-679a-45c2-baf1-2905490ea926@kernel.org> (raw)
In-Reply-To: <17b24b80-c3bb-40a1-ad12-06242ca09c22@oss.nxp.com>
On 04/11/2026 10:41, Larisa Ileana Grigore wrote:
> On 11/4/2026 10:40 AM, Krzysztof Kozlowski wrote:
> v8:
> https://lore.kernel.org/all/20261013103003.373156-1-larisa.grigore@oss.nxp.com/
> v9:
> https://lore.kernel.org/all/20261024122533.3609180-1-larisa.grigore@oss.nxp.com/
> v10:
> https://lore.kernel.org/all/20261103133215.1385823-1-larisa.grigore@oss.nxp.com
>
> Regarding your comments on v9:
>
> Frank's Reviewed-by was given publicly on v8 [1]. The series only looked
> like a v1 because of the wrong version number.
> The tag ordering was changed in v10 since the patch was changed.
> The single 0 Hz OPP entry: as discussed on v8 [2][3], the clock rate is
> set outside Linux and is not scaled. The OPP table lets the UFS core
That is not the purpose of OPP table. OPP defines performance point.
Performance point of 0 makes no sense. You cannot use Linux limitations
as reason to add some DTS, because answer is simple: fix your Linux
limitations.
> enable and gate the clock. As you suggested, v10 explains this in the
> commit message. Let me know if you would like more details there.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-11-05 18:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 13:32 [PATCH v10 00/11] Add S32N79RDB UFS support Larisa Grigore
2026-11-03 13:32 ` [PATCH v10 01/11] ufs: core: Return a negative errno from WLUN suspend/resume Larisa Grigore
2026-11-03 17:53 ` Bart Van Assche
2026-11-03 13:32 ` [PATCH v10 02/11] ufs: dwc: Return a negative error if the link is down Larisa Grigore
2026-11-03 13:32 ` [PATCH v10 03/11] ufs: unipro: Move Tx/Rx FSM state definitions to unipro.h Larisa Grigore
2026-11-03 17:54 ` Bart Van Assche
2026-11-03 13:32 ` [PATCH v10 04/11] ufs: unipro: Add TX/RX FSM state attributes Larisa Grigore
2026-11-03 17:54 ` Bart Van Assche
2026-11-03 13:32 ` [PATCH v10 05/11] ufs: core: Add common Hibern8 TX FSM polling helper Larisa Grigore
2026-11-03 13:32 ` [PATCH v10 06/11] ufs: dwc: Move Versal2 M-PHY CREG access helpers into ufshcd-dwc Larisa Grigore
2026-11-03 13:32 ` [PATCH v10 07/11] ufs: dwc: Export common clock divider and link status helpers Larisa Grigore
2026-11-03 13:32 ` [PATCH v10 08/11] dt-bindings: ufs: Add NXP S32N79 UFS host controller Larisa Grigore
2026-11-04 8:38 ` Krzysztof Kozlowski
2026-11-04 8:40 ` Krzysztof Kozlowski
2026-11-04 9:41 ` Larisa Ileana Grigore
2026-11-05 18:28 ` Krzysztof Kozlowski [this message]
2026-11-03 13:32 ` [PATCH v10 09/11] ufs: dwc: Sort CBCRCTRL and CBREFCLKCTRL2 by offset Larisa Grigore
2026-11-03 13:32 ` [PATCH v10 10/11] ufs: s32n7: Add NXP S32N79 UFS host controller driver Larisa Grigore
2026-11-03 17:57 ` Bart Van Assche
2026-11-03 13:32 ` [PATCH v10 11/11] MAINTAINERS: Add NXP S32N7 UFS host controller entry Larisa Grigore
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