[PATCH 0/4] Adjustments for AMD heterogeneous designs

[PATCH 0/4] Adjustments for AMD heterogeneous designs

[Mario Limonciello]

This series corrects some of the patches that were already queued up for
linux-next and also enables some optimizations for AMD Ryzen AI processors.

This is based off superm1/linux.git linux-next branch and would intend
to merge through this tree with other amd-pstate changes.

Mario Limonciello (3):
  x86/cpufeatures: Rename X86_FEATURE_FAST_CPPC to have AMD prefix
  x86/cpufeatures: Rename X86_FEATURE_HETERO_CORE_TOPOLOGY to
    X86_FEATURE_AMD_HETEROGENEOUS_CORES
  x86/amd: Move AMD core type identification code

Perry Yuan (1):
  x86/cpu: Enable SD_ASYM_PACKING for PKG Domain on AMD Processors

 arch/x86/include/asm/cpufeatures.h       |  4 ++--
 arch/x86/include/asm/processor.h         | 15 +++++++--------
 arch/x86/kernel/acpi/cppc.c              |  2 +-
 arch/x86/kernel/cpu/amd.c                |  9 ++++-----
 arch/x86/kernel/cpu/scattered.c          |  4 ++--
 arch/x86/kernel/smpboot.c                |  5 +++--
 drivers/cpufreq/amd-pstate.c             |  2 +-
 tools/arch/x86/include/asm/cpufeatures.h |  2 +-
 8 files changed, 21 insertions(+), 22 deletions(-)

-- 
2.43.0

[PATCH 1/4] x86/cpufeatures: Rename X86_FEATURE_FAST_CPPC to have AMD prefix

[Mario Limonciello]

This feature is an AMD unique feature of some processors, so put
AMD into the name.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 arch/x86/include/asm/cpufeatures.h       | 2 +-
 arch/x86/kernel/cpu/scattered.c          | 2 +-
 drivers/cpufreq/amd-pstate.c             | 2 +-
 tools/arch/x86/include/asm/cpufeatures.h | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index cea1ed82aeb48..424bb7ae8914a 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -472,7 +472,7 @@
 #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
 #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
 #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
-#define X86_FEATURE_FAST_CPPC		(21*32 + 5) /* AMD Fast CPPC */
+#define X86_FEATURE_AMD_FAST_CPPC		(21*32 + 5) /* Fast CPPC */
 #define X86_FEATURE_HETERO_CORE_TOPOLOGY	(21*32 + 6) /* Heterogeneous Core Topology */
 
 /*
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index 3bba55323163b..d7f2c19abce33 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -45,7 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = {
 	{ X86_FEATURE_HW_PSTATE,	CPUID_EDX,  7, 0x80000007, 0 },
 	{ X86_FEATURE_CPB,		CPUID_EDX,  9, 0x80000007, 0 },
 	{ X86_FEATURE_PROC_FEEDBACK,    CPUID_EDX, 11, 0x80000007, 0 },
-	{ X86_FEATURE_FAST_CPPC, 	CPUID_EDX, 15, 0x80000007, 0 },
+	{ X86_FEATURE_AMD_FAST_CPPC,	CPUID_EDX, 15, 0x80000007, 0 },
 	{ X86_FEATURE_MBA,		CPUID_EBX,  6, 0x80000008, 0 },
 	{ X86_FEATURE_SMBA,		CPUID_EBX,  2, 0x80000020, 0 },
 	{ X86_FEATURE_BMEC,		CPUID_EBX,  3, 0x80000020, 0 },
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 3c14962adeb22..2670bdcad6eda 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -844,7 +844,7 @@ static u32 amd_pstate_get_transition_delay_us(unsigned int cpu)
 
 	transition_delay_ns = cppc_get_transition_latency(cpu);
 	if (transition_delay_ns == CPUFREQ_ETERNAL) {
-		if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC))
+		if (cpu_feature_enabled(X86_FEATURE_AMD_FAST_CPPC))
 			return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY;
 		else
 			return AMD_PSTATE_TRANSITION_DELAY;
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index dd4682857c120..23698d0f4bb47 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -472,7 +472,7 @@
 #define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */
 #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
 #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
-#define X86_FEATURE_FAST_CPPC		(21*32 + 5) /* AMD Fast CPPC */
+#define X86_FEATURE_AMD_FAST_CPPC		(21*32 + 5) /* AMD Fast CPPC */
 
 /*
  * BUG word(s)
-- 
2.43.0

[PATCH 2/4] x86/cpufeatures: Rename X86_FEATURE_HETERO_CORE_TOPOLOGY to X86_FEATURE_AMD_HETEROGENEOUS_CORES

[Mario Limonciello]

X86_FEATURE_AMD_HETEROGENEOUS_CORES makes it clear this is an AMD feature
and matches the APM value of HeterogeneousCores

Suggested-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 arch/x86/include/asm/cpufeatures.h | 2 +-
 arch/x86/kernel/cpu/amd.c          | 2 +-
 arch/x86/kernel/cpu/scattered.c    | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 424bb7ae8914a..7f6c9fc465293 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -473,7 +473,7 @@
 #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
 #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
 #define X86_FEATURE_AMD_FAST_CPPC		(21*32 + 5) /* Fast CPPC */
-#define X86_FEATURE_HETERO_CORE_TOPOLOGY	(21*32 + 6) /* Heterogeneous Core Topology */
+#define X86_FEATURE_AMD_HETEROGENEOUS_CORES	(21*32 + 6) /* Heterogeneous Core Topology */
 
 /*
  * BUG word(s)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 8ad5f1385f0ec..0f533e6260d29 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1223,7 +1223,7 @@ enum amd_core_type amd_get_core_type(void)
 		     core_type                  :4;
 	} props;
 
-	if (!cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY))
+	if (!cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES))
 		return CPU_CORE_TYPE_NO_HETERO_SUP;
 
 	cpuid_leaf_reg(0x80000026, CPUID_EBX, &props);
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index d7f2c19abce33..307a917415343 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -52,7 +52,7 @@ static const struct cpuid_bit cpuid_bits[] = {
 	{ X86_FEATURE_PERFMON_V2,	CPUID_EAX,  0, 0x80000022, 0 },
 	{ X86_FEATURE_AMD_LBR_V2,	CPUID_EAX,  1, 0x80000022, 0 },
 	{ X86_FEATURE_AMD_LBR_PMC_FREEZE,	CPUID_EAX,  2, 0x80000022, 0 },
-	{ X86_FEATURE_HETERO_CORE_TOPOLOGY,	CPUID_EAX,  30, 0x80000026, 0 },
+	{ X86_FEATURE_AMD_HETEROGENEOUS_CORES,	CPUID_EAX,  30, 0x80000026, 0 },
 	{ 0, 0, 0, 0, 0 }
 };
 
-- 
2.43.0

[PATCH 3/4] x86/cpu: Enable SD_ASYM_PACKING for PKG Domain on AMD Processors

[Mario Limonciello]

From: Perry Yuan <perry.yuan@amd.com>

Enable the SD_ASYM_PACKING domain flag for the PKG domain on AMD
heterogeneous processors.
This flag is beneficial for processors with one or more CCDs and
relies on x86_sched_itmt_flags().

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Co-developed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
Rename to match correct x86 feature name
---
 arch/x86/kernel/smpboot.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 766f092dab80b..b5a8f0891135b 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -497,8 +497,9 @@ static int x86_cluster_flags(void)
 
 static int x86_die_flags(void)
 {
-	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
-	       return x86_sched_itmt_flags();
+	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU) ||
+	    cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES))
+		return x86_sched_itmt_flags();
 
 	return 0;
 }
-- 
2.43.0

[PATCH 4/4] x86/amd: Move AMD core type identification code

[Mario Limonciello]

The enum used for AMD core type identification is AMD specific so
it should only be in the definition for CONFIG_CPU_SUP_AMD.

Move the enum into this scope and adjust function return types since
enum amd_core_type won't be available in the non CONFIG_CPU_SUP_AMD
case.  Instead of a dedicated enum definition of no hetero support
use -EINVAL.

Suggested-by: Borislav Petkov <bp@alien8.de>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
---
 arch/x86/include/asm/processor.h | 15 +++++++--------
 arch/x86/kernel/acpi/cppc.c      |  2 +-
 arch/x86/kernel/cpu/amd.c        |  7 +++----
 3 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index d81a6efa81bb0..5b772036f6e83 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -691,15 +691,14 @@ static inline u32 per_cpu_l2c_id(unsigned int cpu)
 	return per_cpu(cpu_info.topo.l2c_id, cpu);
 }
 
+#ifdef CONFIG_CPU_SUP_AMD
 /* defined by CPUID_Fn80000026_EBX BIT [31:28] */
 enum amd_core_type {
-	CPU_CORE_TYPE_NO_HETERO_SUP = -1,
-	CPU_CORE_TYPE_PERFORMANCE = 0,
-	CPU_CORE_TYPE_EFFICIENCY = 1,
-	CPU_CORE_TYPE_UNDEFINED = 2,
+	CPU_CORE_TYPE_PERFORMANCE,
+	CPU_CORE_TYPE_EFFICIENCY,
+	CPU_CORE_TYPE_UNDEFINED,
 };
 
-#ifdef CONFIG_CPU_SUP_AMD
 /*
  * Issue a DIV 0/1 insn to clear any division data from previous DIV
  * operations.
@@ -711,13 +710,13 @@ static __always_inline void amd_clear_divider(void)
 }
 
 extern void amd_check_microcode(void);
-extern enum amd_core_type amd_get_core_type(void);
+extern int amd_get_core_type(void);
 #else
 static inline void amd_clear_divider(void)		{ }
 static inline void amd_check_microcode(void)		{ }
-static inline enum amd_core_type amd_get_core_type(void)
+static inline int amd_get_core_type(void)
 {
-	return CPU_CORE_TYPE_NO_HETERO_SUP;
+	return -EINVAL;
 }
 #endif
 
diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
index ca289e6ec82c9..e25494212d964 100644
--- a/arch/x86/kernel/acpi/cppc.c
+++ b/arch/x86/kernel/acpi/cppc.c
@@ -273,7 +273,7 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator)
 	/* detect if running on heterogeneous design */
 	smp_call_function_single(cpu, amd_do_get_core_type, &core_type, 1);
 	switch (core_type) {
-	case CPU_CORE_TYPE_NO_HETERO_SUP:
+	case -EINVAL:
 		break;
 	case CPU_CORE_TYPE_PERFORMANCE:
 		/* use the max scale for performance cores */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 0f533e6260d29..a0d17993d52ce 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1211,10 +1211,9 @@ void amd_check_microcode(void)
  * Returns the CPU type [31:28] (i.e., performance or efficient) of
  * a CPU in the processor.
  *
- * If the processor has no core type support, returns
- * CPU_CORE_TYPE_NO_HETERO_SUP.
+ * If the processor has no core type support, returns -EINVAL.
  */
-enum amd_core_type amd_get_core_type(void)
+int amd_get_core_type(void)
 {
 	struct {
 		u32  num_processors             :16,
@@ -1224,7 +1223,7 @@ enum amd_core_type amd_get_core_type(void)
 	} props;
 
 	if (!cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES))
-		return CPU_CORE_TYPE_NO_HETERO_SUP;
+		return -EINVAL;
 
 	cpuid_leaf_reg(0x80000026, CPUID_EBX, &props);
 	if (props.core_type >= CPU_CORE_TYPE_UNDEFINED)
-- 
2.43.0

Re: [PATCH 2/4] x86/cpufeatures: Rename X86_FEATURE_HETERO_CORE_TOPOLOGY to X86_FEATURE_AMD_HETEROGENEOUS_CORES

[Mario Limonciello]

On 10/21/2024 12:55, Mario Limonciello wrote:
> X86_FEATURE_AMD_HETEROGENEOUS_CORES makes it clear this is an AMD feature
> and matches the APM value of HeterogeneousCores
> 
> Suggested-by: Borislav Petkov <bp@alien8.de>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
>   arch/x86/include/asm/cpufeatures.h | 2 +-
>   arch/x86/kernel/cpu/amd.c          | 2 +-
>   arch/x86/kernel/cpu/scattered.c    | 2 +-
>   3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 424bb7ae8914a..7f6c9fc465293 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -473,7 +473,7 @@
>   #define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */
>   #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */
>   #define X86_FEATURE_AMD_FAST_CPPC		(21*32 + 5) /* Fast CPPC */
> -#define X86_FEATURE_HETERO_CORE_TOPOLOGY	(21*32 + 6) /* Heterogeneous Core Topology */
> +#define X86_FEATURE_AMD_HETEROGENEOUS_CORES	(21*32 + 6) /* Heterogeneous Core Topology */
>   
>   /*
>    * BUG word(s)
> diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
> index 8ad5f1385f0ec..0f533e6260d29 100644
> --- a/arch/x86/kernel/cpu/amd.c
> +++ b/arch/x86/kernel/cpu/amd.c
> @@ -1223,7 +1223,7 @@ enum amd_core_type amd_get_core_type(void)
>   		     core_type                  :4;
>   	} props;
>   
> -	if (!cpu_feature_enabled(X86_FEATURE_HETERO_CORE_TOPOLOGY))
> +	if (!cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES))
>   		return CPU_CORE_TYPE_NO_HETERO_SUP;
>   
>   	cpuid_leaf_reg(0x80000026, CPUID_EBX, &props);
> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> index d7f2c19abce33..307a917415343 100644
> --- a/arch/x86/kernel/cpu/scattered.c
> +++ b/arch/x86/kernel/cpu/scattered.c
> @@ -52,7 +52,7 @@ static const struct cpuid_bit cpuid_bits[] = {
>   	{ X86_FEATURE_PERFMON_V2,	CPUID_EAX,  0, 0x80000022, 0 },
>   	{ X86_FEATURE_AMD_LBR_V2,	CPUID_EAX,  1, 0x80000022, 0 },
>   	{ X86_FEATURE_AMD_LBR_PMC_FREEZE,	CPUID_EAX,  2, 0x80000022, 0 },
> -	{ X86_FEATURE_HETERO_CORE_TOPOLOGY,	CPUID_EAX,  30, 0x80000026, 0 },
> +	{ X86_FEATURE_AMD_HETEROGENEOUS_CORES,	CPUID_EAX,  30, 0x80000026, 0 },
>   	{ 0, 0, 0, 0, 0 }
>   };
>   


I talked to Boris offline about this and I misinterpreted Rafael's 
intent with "the former".  The original patches will need to be dropped 
and I will redo patches 2 and 4 in this series considering that.