From: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com,
mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org,
kishon@kernel.org, neil.armstrong@linaro.org,
abel.vesa@linaro.org, kw@linux.com,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com,
krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com
Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: Add PCIe3 and PCIe5 regulators for HAMAO-IOT-EVK board
Date: Tue, 18 Nov 2025 18:11:47 +0800 [thread overview]
Message-ID: <12bce4de-9491-4040-991b-529bc916983c@oss.qualcomm.com> (raw)
In-Reply-To: <rakvukrdsb3vpr4k22hgvbr2yc65me32uezwrqgn2573kblirt@7q7pgr3nkvso>
On 11/13/2025 5:16 AM, Dmitry Baryshkov wrote:
> On Wed, Nov 12, 2025 at 05:03:16PM +0800, Ziyue Zhang wrote:
>> HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality
>> and PCIe3 to connect a SATA controller. These interfaces require multiple
>> voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires
>> 12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs.
>>
>> Add the required fixed regulators with related pin configuration, and
>> connect them to the PCIe3 and PCIe5 ports to ensure proper power for the
>> SDX65 module and SATA controller.
>>
>> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
>> Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 83 ++++++++++++++++++++++
>> 1 file changed, 83 insertions(+)
>>
>> +&pmc8380_3_gpios {
>> + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state {
> What is sde7? Other than that:
>
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>
Hi Dmitry
I’m not sure what “sde7” refers to specifically. I saw this name in the
schematic, and the pin is labeled PM_SDE7_AUX_3P3, so I used that naming
in the DT.
BRs
Ziyue
>
>> + pins = "gpio8";
>> + function = "normal";
>> + output-enable;
>> + output-high;
>> + bias-pull-down;
>> + power-source = <0>;
>> + };
>> +
>> + pm_sde7_main_3p3_en: pcie-main-3p3-default-state {
>> + pins = "gpio6";
>> + function = "normal";
>> + output-enable;
>> + output-high;
>> + bias-pull-down;
>> + power-source = <0>;
>> + };
>> +};
>> +
>> &pmc8380_5_gpios {
>> usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state {
>> pins = "gpio8";
>> --
>> 2.34.1
>>
next prev parent reply other threads:[~2025-11-18 10:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-12 9:03 [PATCH v3 0/2] Add PCIe3 and PCIe5 support for HAMOA-IOT-EVK board Ziyue Zhang
2025-11-12 9:03 ` [PATCH v3 1/2] arm64: dts: qcom: Add PCIe3 and PCIe5 support for HAMOA-IOT-SOM platform Ziyue Zhang
2025-11-12 21:15 ` Dmitry Baryshkov
2025-11-13 4:51 ` Manivannan Sadhasivam
2025-11-12 9:03 ` [PATCH v3 2/2] arm64: dts: qcom: Add PCIe3 and PCIe5 regulators for HAMAO-IOT-EVK board Ziyue Zhang
2025-11-12 16:33 ` Bjorn Andersson
2025-11-12 21:16 ` Dmitry Baryshkov
2025-11-18 10:11 ` Ziyue Zhang [this message]
2025-11-18 10:23 ` Konrad Dybcio
2025-11-18 11:00 ` Dmitry Baryshkov
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