From: Andi Kleen <andi@firstfloor.org>
To: mingo@elte.hu
Cc: linux-kernel@vger.kernel.org, a.p.zijlstra@chello.nl,
akpm@linux-foundation.org, acme@redhat.com, eranian@google.com,
jolsa@redhat.com, namhyung@kernel.org,
Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 03/29] perf, x86: Basic Haswell PEBS support v3
Date: Thu, 17 Jan 2013 12:36:26 -0800 [thread overview]
Message-ID: <1358455012-12287-4-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1358455012-12287-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
Add basic PEBS support for Haswell.
The constraints are similar to SandyBridge with a few new events.
v2: Readd missing pebs_aliases
v3: Readd missing hunk. Fix some constraints.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event.h | 2 ++
arch/x86/kernel/cpu/perf_event_intel.c | 6 ++++--
arch/x86/kernel/cpu/perf_event_intel_ds.c | 29 +++++++++++++++++++++++++++++
3 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 8941899..1567b0d 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -596,6 +596,8 @@ extern struct event_constraint intel_snb_pebs_event_constraints[];
extern struct event_constraint intel_ivb_pebs_event_constraints[];
+extern struct event_constraint intel_hsw_pebs_event_constraints[];
+
struct event_constraint *intel_pebs_constraints(struct perf_event *event);
void intel_pmu_pebs_enable(struct perf_event *event);
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 3a08534..634f639 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -826,7 +826,8 @@ static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
return true;
/* implicit branch sampling to correct PEBS skid */
- if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
+ if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
+ x86_pmu.intel_cap.pebs_format < 2)
return true;
return false;
@@ -2127,8 +2128,9 @@ __init int intel_pmu_init(void)
intel_pmu_lbr_init_nhm();
x86_pmu.event_constraints = intel_hsw_event_constraints;
-
+ x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
x86_pmu.extra_regs = intel_snb_extra_regs;
+ x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
/* all extra regs are per-cpu when HT is on */
x86_pmu.er_flags |= ERF_HAS_RSP_1;
x86_pmu.er_flags |= ERF_NO_HT_SHARING;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 9d0dae0..16d7c58 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -427,6 +427,35 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
EVENT_CONSTRAINT_END
};
+struct event_constraint intel_hsw_pebs_event_constraints[] = {
+ INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
+ INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
+ INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
+ INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
+ INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
+ INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
+ INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
+ INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.* */
+ INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
+ INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
+ INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
+ INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
+ INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
+ INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
+ INTEL_UEVENT_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
+ INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
+ INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
+ INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
+ INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
+ INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
+ INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
+ INTEL_UEVENT_CONSTRAINT(0x02d3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
+ INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
+ INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
+
+ EVENT_CONSTRAINT_END
+};
+
struct event_constraint *intel_pebs_constraints(struct perf_event *event)
{
struct event_constraint *c;
--
1.7.7.6
next prev parent reply other threads:[~2013-01-17 20:38 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-17 20:36 perf PMU support for Haswell v7 Andi Kleen
2013-01-17 20:36 ` [PATCH 01/29] perf, x86: Add PEBSv2 record support Andi Kleen
2013-01-17 20:36 ` [PATCH 02/29] perf, x86: Basic Haswell PMU support v2 Andi Kleen
2013-01-17 20:36 ` Andi Kleen [this message]
2013-01-17 20:36 ` [PATCH 04/29] perf, x86: Support the TSX intx/intx_cp qualifiers v2 Andi Kleen
2013-01-17 20:36 ` [PATCH 05/29] perf, kvm: Support the intx/intx_cp modifiers in KVM arch perfmon emulation v4 Andi Kleen
2013-01-20 14:04 ` Gleb Natapov
2013-01-17 20:36 ` [PATCH 06/29] perf, x86: Support PERF_SAMPLE_ADDR on Haswell Andi Kleen
2013-01-17 20:36 ` [PATCH 07/29] perf, x86: Support Haswell v4 LBR format Andi Kleen
2013-01-17 20:36 ` [PATCH 08/29] perf, x86: Disable LBR recording for unknown LBR_FMT Andi Kleen
2013-01-17 20:36 ` [PATCH 09/29] perf, x86: Support LBR filtering by INTX/NOTX/ABORT v2 Andi Kleen
2013-01-17 20:36 ` [PATCH 10/29] perf, tools: Add abort_tx,no_tx,in_tx branch filter options to perf record -j v3 Andi Kleen
2013-01-17 20:36 ` [PATCH 11/29] perf, tools: Support sorting by intx, abort branch flags v2 Andi Kleen
2013-01-17 20:36 ` [PATCH 12/29] perf, x86: Support full width counting Andi Kleen
2013-01-17 20:36 ` [PATCH 13/29] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v3 Andi Kleen
2013-01-17 20:36 ` [PATCH 14/29] perf, core: Add a concept of a weightened sample v2 Andi Kleen
2013-01-17 20:36 ` [PATCH 15/29] perf, x86: Support weight samples for PEBS Andi Kleen
2013-01-17 20:36 ` [PATCH 16/29] perf, tools: Add support for weight v7 Andi Kleen
2013-01-23 11:38 ` Stephane Eranian
2013-01-23 11:54 ` Stephane Eranian
2013-01-23 16:56 ` Andi Kleen
2013-01-23 17:00 ` Stephane Eranian
2013-01-23 17:13 ` Andi Kleen
2013-01-23 17:25 ` Stephane Eranian
2013-01-23 18:02 ` Andi Kleen
2013-01-23 18:18 ` Stephane Eranian
2013-01-23 18:50 ` Andi Kleen
2013-01-23 18:57 ` Stephane Eranian
2013-01-17 20:36 ` [PATCH 17/29] perf, core: Add generic transaction flags v3 Andi Kleen
2013-01-17 20:36 ` [PATCH 18/29] perf, x86: Add Haswell specific transaction flag reporting Andi Kleen
2013-01-17 20:36 ` [PATCH 19/29] perf, tools: Add support for record transaction flags v3 Andi Kleen
2013-01-17 20:36 ` [PATCH 20/29] perf, tools: Add browser support for transaction flags v5 Andi Kleen
2013-01-17 20:36 ` [PATCH 21/29] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-01-17 20:36 ` [PATCH 22/29] tools, perf: Add a precise event qualifier v2 Andi Kleen
2013-01-17 20:36 ` [PATCH 23/29] perf, x86: improve sysfs event mapping with event string Andi Kleen
2013-01-17 20:36 ` [PATCH 24/29] perf, x86: Support CPU specific sysfs events Andi Kleen
2013-01-17 20:36 ` [PATCH 25/29] perf, x86: Add Haswell TSX event aliases v2 Andi Kleen
2013-01-17 20:36 ` [PATCH 26/29] perf, tools: Add perf stat --transaction v2 Andi Kleen
2013-01-17 20:36 ` [PATCH 27/29] perf, x86: Add a Haswell precise instructions event v2 Andi Kleen
2013-01-17 20:36 ` [PATCH 28/29] perf, tools: Default to cpu// for events v5 Andi Kleen
2013-01-17 20:36 ` [PATCH 29/29] perf, tools: List kernel supplied event aliases in perf list v2 Andi Kleen
2013-01-24 11:39 ` perf PMU support for Haswell v7 Ingo Molnar
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