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From: Andi Kleen <andi@firstfloor.org>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, peterz@infradead.org,
	Andi Kleen <ak@linux.intel.com>,
	bp@suse.de
Subject: [PATCH 1/6] perf, x86, amd: Move __get_ibs_caps into common amd CPU file
Date: Fri,  4 Oct 2013 14:39:43 -0700	[thread overview]
Message-ID: <1380922788-23112-2-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1380922788-23112-1-git-send-email-andi@firstfloor.org>

From: Andi Kleen <ak@linux.intel.com>

__get_ibs_caps is used by both oprofile and perf events.
This causes oprofile to be dependent on perf.

__get_ibs_caps is actually only a few lines, so we can
easily move that to the standard AMD CPU initialization
file.

It will be always compiled in this way, but it's far
better than requiring perf always to be compiled in for this.

Cc: bp@suse.de
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/include/asm/perf_event.h        |  2 ++
 arch/x86/kernel/cpu/amd.c                | 27 +++++++++++++++++++++++++++
 arch/x86/kernel/cpu/perf_event_amd_ibs.c | 23 -----------------------
 arch/x86/oprofile/op_model_amd.c         |  4 +++-
 4 files changed, 32 insertions(+), 24 deletions(-)

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 8249df4..866b0f3 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -198,6 +198,8 @@ struct x86_pmu_capability {
 #define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
 #define IBS_RIP_INVALID		(1ULL<<38)
 
+extern u32 __get_ibs_caps(void);
+
 #ifdef CONFIG_X86_LOCAL_APIC
 extern u32 get_ibs_caps(void);
 #else
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 903a264..887ad1e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -16,6 +16,8 @@
 # include <asm/cacheflush.h>
 #endif
 
+#include <asm/perf_event.h>
+
 #include "cpu.h"
 
 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
@@ -909,3 +911,28 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
 
 	return false;
 }
+
+
+/* IBS - apic initialization, for perf and oprofile */
+
+u32 __get_ibs_caps(void)
+{
+	u32 caps;
+	unsigned int max_level;
+
+	if (!boot_cpu_has(X86_FEATURE_IBS))
+		return 0;
+
+	/* check IBS cpuid feature flags */
+	max_level = cpuid_eax(0x80000000);
+	if (max_level < IBS_CPUID_FEATURES)
+		return IBS_CAPS_DEFAULT;
+
+	caps = cpuid_eax(IBS_CPUID_FEATURES);
+	if (!(caps & IBS_CAPS_AVAIL))
+		/* cpuid flags not valid */
+		return IBS_CAPS_DEFAULT;
+
+	return caps;
+}
+EXPORT_SYMBOL(__get_ibs_caps);
diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
index e09f0bf..c4fed71 100644
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -664,29 +664,6 @@ static __init int perf_event_ibs_init(void) { return 0; }
 
 #endif
 
-/* IBS - apic initialization, for perf and oprofile */
-
-static __init u32 __get_ibs_caps(void)
-{
-	u32 caps;
-	unsigned int max_level;
-
-	if (!boot_cpu_has(X86_FEATURE_IBS))
-		return 0;
-
-	/* check IBS cpuid feature flags */
-	max_level = cpuid_eax(0x80000000);
-	if (max_level < IBS_CPUID_FEATURES)
-		return IBS_CAPS_DEFAULT;
-
-	caps = cpuid_eax(IBS_CPUID_FEATURES);
-	if (!(caps & IBS_CAPS_AVAIL))
-		/* cpuid flags not valid */
-		return IBS_CAPS_DEFAULT;
-
-	return caps;
-}
-
 u32 get_ibs_caps(void)
 {
 	return ibs_caps;
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 50d86c0..964171f 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -26,6 +26,8 @@
 #include <asm/processor.h>
 #include <asm/cpufeature.h>
 
+#include <asm/perf_event.h> /* for __get_ibs_caps */
+
 #include "op_x86_model.h"
 #include "op_counter.h"
 
@@ -446,7 +448,7 @@ static void op_amd_stop(struct op_msrs const * const msrs)
 
 static void init_ibs(void)
 {
-	ibs_caps = get_ibs_caps();
+	ibs_caps = __get_ibs_caps();
 
 	if (!ibs_caps)
 		return;
-- 
1.8.3.1


  reply	other threads:[~2013-10-04 21:41 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-10-04 21:39 Allow disabling perf on x86 Andi Kleen
2013-10-04 21:39 ` Andi Kleen [this message]
2013-10-04 21:39 ` [PATCH 2/6] perf, x86: Make perf amd ibs code depend on PERF_EVENTS and SUP_AMD Andi Kleen
2013-10-04 21:39 ` [PATCH 3/6] x86, ptrace: Ifdef HW_BREAKPOINTS code in ptrace Andi Kleen
2013-10-04 21:39 ` [PATCH 4/6] trace: Make UPROBES depend on PERF_EVENTS Andi Kleen
2013-10-05  0:52   ` Steven Rostedt
2013-10-05  3:25     ` Andi Kleen
2013-10-04 21:39 ` [PATCH 5/6] x86, kgdb: Support compiling without hardware break points Andi Kleen
2013-10-04 21:39 ` [PATCH 6/6] x86: Allow disabling HW_BREAKPOINTS and PERF_EVENTS Andi Kleen
2013-10-04 22:27   ` Frederic Weisbecker
2013-10-05  7:08   ` Ingo Molnar
2013-10-05 17:05     ` Andi Kleen
2013-10-08 19:55       ` Frederic Weisbecker
2013-10-08 20:05         ` Peter Zijlstra
2013-10-08 20:34           ` Frederic Weisbecker
2013-10-08 20:35           ` Frederic Weisbecker
2013-10-09  6:02             ` Ingo Molnar
2013-10-06 16:49   ` Ingo Molnar
2013-10-08  6:59     ` Ingo Molnar
2013-10-08 15:35       ` Steven Rostedt
2013-10-08 19:39         ` Ingo Molnar
2013-10-08 15:42       ` Vince Weaver
2013-10-08 15:51       ` Dave Jones
2013-10-08 16:22         ` David Ahern
2013-10-08 16:24           ` Dave Jones
2013-10-08 19:36             ` Ingo Molnar
2013-10-08 20:19               ` Steven Rostedt
2013-10-09  3:21             ` Andi Kleen
2013-10-09  3:24       ` Andi Kleen
2013-10-09  3:39       ` Andi Kleen

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