From: Andi Kleen <andi@firstfloor.org>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, peterz@infradead.org,
Andi Kleen <ak@linux.intel.com>,
fweisbec@gmail.com
Subject: [PATCH 3/6] x86, ptrace: Ifdef HW_BREAKPOINTS code in ptrace
Date: Fri, 4 Oct 2013 14:39:45 -0700 [thread overview]
Message-ID: <1380922788-23112-4-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1380922788-23112-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
Add ifdefs on CONFIG_HW_BREAKPOINTS to the hardware
break point code in x86 ptrace.c. This prepares
this file for being able to disable HW_BREAKPOINTS.
The only debug register that needs to be handled
without break points is DR6, so do that in a simple
separate function without breakpoints.
Cc: fweisbec@gmail.com
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/ptrace.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 7461f50..dda433f 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -561,6 +561,8 @@ static int genregs_set(struct task_struct *target,
return ret;
}
+#ifdef CONFIG_HW_BREAKPOINTS
+
static void ptrace_triggered(struct perf_event *bp,
struct perf_sample_data *data,
struct pt_regs *regs)
@@ -778,6 +780,34 @@ static int ptrace_set_debugreg(struct task_struct *tsk, int n,
return rc;
}
+#else
+
+/* Without breakpoints only handle DR6 */
+static unsigned long ptrace_get_debugreg(struct task_struct *tsk, int n)
+{
+ struct thread_struct *thread = &tsk->thread;
+
+ if (n == 6)
+ return thread->debugreg6;
+ return 0;
+}
+
+/* Without breakpoints only handle DR6 */
+static int ptrace_set_debugreg(struct task_struct *tsk, int n,
+ unsigned long val)
+{
+ struct thread_struct *thread = &tsk->thread;
+ int rc = -EIO;
+
+ if (n == 6) {
+ thread->debugreg6 = val;
+ rc = 0;
+ }
+ return rc;
+}
+
+#endif
+
/*
* These access the current or another (stopped) task's io permission
* bitmap for debugging or core dump.
--
1.8.3.1
next prev parent reply other threads:[~2013-10-04 21:39 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-04 21:39 Allow disabling perf on x86 Andi Kleen
2013-10-04 21:39 ` [PATCH 1/6] perf, x86, amd: Move __get_ibs_caps into common amd CPU file Andi Kleen
2013-10-04 21:39 ` [PATCH 2/6] perf, x86: Make perf amd ibs code depend on PERF_EVENTS and SUP_AMD Andi Kleen
2013-10-04 21:39 ` Andi Kleen [this message]
2013-10-04 21:39 ` [PATCH 4/6] trace: Make UPROBES depend on PERF_EVENTS Andi Kleen
2013-10-05 0:52 ` Steven Rostedt
2013-10-05 3:25 ` Andi Kleen
2013-10-04 21:39 ` [PATCH 5/6] x86, kgdb: Support compiling without hardware break points Andi Kleen
2013-10-04 21:39 ` [PATCH 6/6] x86: Allow disabling HW_BREAKPOINTS and PERF_EVENTS Andi Kleen
2013-10-04 22:27 ` Frederic Weisbecker
2013-10-05 7:08 ` Ingo Molnar
2013-10-05 17:05 ` Andi Kleen
2013-10-08 19:55 ` Frederic Weisbecker
2013-10-08 20:05 ` Peter Zijlstra
2013-10-08 20:34 ` Frederic Weisbecker
2013-10-08 20:35 ` Frederic Weisbecker
2013-10-09 6:02 ` Ingo Molnar
2013-10-06 16:49 ` Ingo Molnar
2013-10-08 6:59 ` Ingo Molnar
2013-10-08 15:35 ` Steven Rostedt
2013-10-08 19:39 ` Ingo Molnar
2013-10-08 15:42 ` Vince Weaver
2013-10-08 15:51 ` Dave Jones
2013-10-08 16:22 ` David Ahern
2013-10-08 16:24 ` Dave Jones
2013-10-08 19:36 ` Ingo Molnar
2013-10-08 20:19 ` Steven Rostedt
2013-10-09 3:21 ` Andi Kleen
2013-10-09 3:24 ` Andi Kleen
2013-10-09 3:39 ` Andi Kleen
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