From: Daniel Thompson <daniel.thompson@linaro.org>
To: Russell King <linux@arm.linux.org.uk>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Cc: Daniel Thompson <daniel.thompson@linaro.org>,
Marex Vasut <marex@denx.de>, Harro Haan <hrhaan@gmail.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, patches@linaro.org,
linaro-kernel@lists.linaro.org,
John Stultz <john.stultz@linaro.org>,
Peter De Schrijver <pdeschrijver@nvidia.com>
Subject: [PATCH RFC 3/9] irqchip: gic: Remove spin locks from eoi_irq
Date: Mon, 21 Jul 2014 15:47:14 +0100 [thread overview]
Message-ID: <1405954040-30399-4-git-send-email-daniel.thompson@linaro.org> (raw)
In-Reply-To: <1405954040-30399-1-git-send-email-daniel.thompson@linaro.org>
This patch is motivated by the comment it removes from gic_init_fiq,
namely that the spin locks in eoi_irq preclude certain platforms from
supporting FIQ.
Currently there is only one upstream platform (tegra) that actually
hooks gic_arch_extn.irq_eoi and it does not require these spin locks.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/irqchip/irq-gic.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d3c7559..5c934a4 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -191,11 +191,8 @@ static void gic_unmask_irq(struct irq_data *d)
static void gic_eoi_irq(struct irq_data *d)
{
- if (gic_arch_extn.irq_eoi) {
- raw_spin_lock(&irq_controller_lock);
+ if (gic_arch_extn.irq_eoi)
gic_arch_extn.irq_eoi(d);
- raw_spin_unlock(&irq_controller_lock);
- }
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
}
@@ -437,13 +434,6 @@ static void __init gic_init_fiq(struct gic_chip_data *gic,
unsigned int i;
/*
- * FIQ can only be supported on platforms without an extended irq_eoi
- * method (otherwise we take a lock during eoi handling).
- */
- if (gic_arch_extn.irq_eoi)
- return;
-
- /*
* If grouping is not available (not implemented or prohibited by
* security mode) these registers a read-as-zero/write-ignored.
* However as a precaution we restore the reset default regardless of
--
1.9.3
next prev parent reply other threads:[~2014-07-21 14:48 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-21 14:47 [PATCH RFC 0/9] Fix INTACK for FIQ support on ARM Cortex A9 Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 1/9] irqchip: gic: Provide support for interrupt grouping Daniel Thompson
2014-07-21 16:07 ` Marek Vasut
2014-07-21 14:47 ` [PATCH RFC 2/9] irqchip: gic: Add support for FIQ management Daniel Thompson
2014-07-21 14:47 ` Daniel Thompson [this message]
2014-07-21 14:47 ` [PATCH RFC 4/9] ARM: dump the status of NS bit in L1 PTE Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 5/9] ARM: Add L1 PTE non-secure mapping Daniel Thompson
2014-07-21 16:46 ` Russell King - ARM Linux
2014-07-22 10:16 ` Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 6/9] arm: mm: Avoid ioremap_page_range() for non-secure mappings Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 7/9] irqchip: gic: Use non-secure aliased register set when FIQ is enabled Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 8/9] ARM: socfpga: Map the GIC CPU registers as MT_DEVICE_NS Daniel Thompson
2014-07-21 14:47 ` [PATCH RFC 9/9] arm: imx: non-secure aliased mapping of GIC registers Daniel Thompson
2014-07-21 16:15 ` Marek Vasut
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