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From: Andi Kleen <andi@firstfloor.org>
To: x86@kernel.org
Cc: luto@kernel.org, linux-kernel@vger.kernel.org,
	Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 5/8] x86: Make old K8 swapgs workaround conditional
Date: Fri, 10 Apr 2015 08:50:30 -0700	[thread overview]
Message-ID: <1428681033-1549-6-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1428681033-1549-1-git-send-email-andi@firstfloor.org>

From: Andi Kleen <ak@linux.intel.com>

Every gs selector/index reload always paid an extra MFENCE
between the two SWAPGS. This was to work around an old
bug in early K8 steppings.  All other CPUs don't need the extra
mfence. Patch the extra MFENCE only in for K8.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/include/asm/cpufeature.h |  1 +
 arch/x86/kernel/cpu/amd.c         |  3 +++
 arch/x86/kernel/entry_64.S        | 10 +++++++++-
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 90a5485..c695fad 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -255,6 +255,7 @@
 #define X86_BUG_11AP		X86_BUG(5) /* Bad local APIC aka 11AP */
 #define X86_BUG_FXSAVE_LEAK	X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
 #define X86_BUG_CLFLUSH_MONITOR	X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
+#define X86_BUG_SWAPGS_MFENCE	X86_BUG(8) /* SWAPGS may need MFENCE */
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index a220239..e7f5667 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -551,6 +551,9 @@ static void init_amd_k8(struct cpuinfo_x86 *c)
 	if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 
+	/* Early steppings needed a mfence on swapgs. */
+	set_cpu_cap(c, X86_BUG_SWAPGS_MFENCE);
+
 	/*
 	 * Some BIOSes incorrectly force this feature, but only K8 revision D
 	 * (model = 0x14) and later actually support it.
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 0b74ab0..bb44292 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1212,13 +1212,21 @@ ENTRY(native_load_gs_index)
 	SWAPGS
 gs_change:
 	movl %edi,%gs
-2:	mfence		/* workaround */
+2:	ASM_NOP3	/* may be replaced with mfence */
 	SWAPGS
 	popfq_cfi
 	ret
 	CFI_ENDPROC
 END(native_load_gs_index)
 
+	/* Early K8 systems needed an mfence after swapgs to workaround a bug */
+	.section .altinstr_replacement,"ax"
+3:	mfence
+	.previous
+	.section .altinstructions,"a"
+	altinstruction_entry 2b,3b,X86_BUG_SWAPGS_MFENCE,3,3
+	.previous
+
 	_ASM_EXTABLE(gs_change,bad_gs)
 	.section .fixup,"ax"
 	/* running with kernelgs */
-- 
1.9.3


  parent reply	other threads:[~2015-04-10 15:52 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-10 15:50 Updated RD/WRFS/GSBASE patchkit Andi Kleen
2015-04-10 15:50 ` [PATCH 1/8] percpu: Add a DEFINE_PER_CPU_2PAGE_ALIGNED Andi Kleen
2015-04-10 15:50 ` [PATCH 2/8] x86: Naturally align the debug IST stack Andi Kleen
2015-04-10 18:50   ` Andy Lutomirski
2015-04-10 15:50 ` [PATCH 3/8] x86: Add intrinsics/macros for new rd/wr fs/gs base instructions Andi Kleen
2015-04-10 19:06   ` Andy Lutomirski
2015-04-10 19:07   ` Andy Lutomirski
2015-04-10 15:50 ` [PATCH 4/8] x86: Add support for rd/wr fs/gs base Andi Kleen
2015-04-10 19:12   ` Andy Lutomirski
2015-04-10 20:21     ` Andi Kleen
2015-04-10 20:25       ` Borislav Petkov
2015-04-10 20:52         ` Andi Kleen
2015-04-10 20:53           ` Borislav Petkov
2015-04-10 20:34       ` Andy Lutomirski
2015-04-10 20:41         ` Andi Kleen
2015-04-10 20:47           ` Andy Lutomirski
2015-04-10 20:57             ` Andi Kleen
2015-04-10 21:07               ` Andy Lutomirski
2015-04-10 22:52             ` Andi Kleen
2015-04-10 23:00               ` Andy Lutomirski
2015-04-10 23:05                 ` Andi Kleen
2015-04-10 23:15                   ` Andy Lutomirski
2015-04-10 23:18                     ` Andi Kleen
2015-04-10 23:21                       ` Andy Lutomirski
2015-04-10 23:16                   ` Andi Kleen
2015-04-13  7:07                   ` Jan Beulich
2015-04-10 15:50 ` Andi Kleen [this message]
2015-04-10 21:46   ` [PATCH 5/8] x86: Make old K8 swapgs workaround conditional Andy Lutomirski
2015-04-10 22:01   ` Borislav Petkov
2015-04-10 23:10     ` Andi Kleen
2015-04-11  7:18       ` Borislav Petkov
2015-04-10 15:50 ` [PATCH 6/8] x86: Enumerate kernel FSGS capability in AT_HWCAP2 Andi Kleen
2015-04-10 19:15   ` Andy Lutomirski
2015-04-10 22:14   ` Borislav Petkov
2015-04-10 23:07     ` Andi Kleen
2015-04-10 23:08     ` Andi Kleen
2015-04-11  7:16       ` Borislav Petkov
2015-04-11  8:35         ` Intel FSGSBASE support (was: Re: [PATCH 6/8] x86: Enumerate kernel FSGS capability in AT_HWCAP2) Ingo Molnar
2015-04-10 15:50 ` [PATCH 7/8] x86: Add documentation for rd/wr fs/gs base Andi Kleen
2015-04-10 19:17   ` Andy Lutomirski
2015-04-10 20:22     ` Andi Kleen
2015-04-10 20:38       ` Andy Lutomirski
2015-04-10 20:46         ` Andi Kleen
2015-04-10 20:52           ` Andy Lutomirski
2015-04-10 15:50 ` [PATCH 8/8] x86: Use rd/wr fs/gs base in arch_prctl Andi Kleen
2015-04-10 19:19   ` Andy Lutomirski
2015-04-10 19:58     ` Andi Kleen
  -- strict thread matches above, loose matches on Subject: below --
2014-11-10 23:55 [PATCH 1/8] percpu: Add a DEFINE_PER_CPU_2PAGE_ALIGNED Andi Kleen
2014-11-10 23:55 ` [PATCH 5/8] x86: Make old K8 swapgs workaround conditional Andi Kleen
2014-11-11 20:06   ` Andy Lutomirski
2014-10-15  5:11 [PATCH 1/8] percpu: Add a DEFINE_PER_CPU_2PAGE_ALIGNED Andi Kleen
2014-10-15  5:11 ` [PATCH 5/8] x86: Make old K8 swapgs workaround conditional Andi Kleen

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