From: Andi Kleen <ak@linux.intel.com>
To: Andy Lutomirski <luto@amacapital.net>
Cc: Andi Kleen <andi@firstfloor.org>, X86 ML <x86@kernel.org>,
Andrew Lutomirski <luto@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Steven Rostedt <rostedt@goodmis.org>,
Borislav Petkov <bp@alien8.de>
Subject: Re: [PATCH 4/8] x86: Add support for rd/wr fs/gs base
Date: Fri, 10 Apr 2015 13:21:32 -0700 [thread overview]
Message-ID: <20150410202132.GQ15335@tassilo.jf.intel.com> (raw)
In-Reply-To: <CALCETrU1c=SmGgOXof6VC_EsH_gQwCHGoajnDCJccnQustVyiA@mail.gmail.com>
> We never run paranoid_exit if we interrupted userspace, and we can't
> context switch on the IST stack, so I don't see how this is possible.
>
> > - Restore from R15 (with FSGSBASE), if the gs base was saved
> > in R15
>
> What about case 4: we interrupted the kernel with usergs? (The code
> seems more correct in this regard, but this description above is
> confusing to me.)
I'll fix the description.
> > estacks = per_cpu(debug_stack, cpu);
> > + /* Store GS at bottom of stack for bootstrap access */
> > + *(void **)estacks = gs;
> > estacks += exception_stack_sizes[v];
> > oist->ist[v] = t->x86_tss.ist[v] =
> > (unsigned long)estacks;
>
> Seems reasonable to me.
>
> You could possibly simplify some things if you wrote the address to
> the bottom of *each* debug stack. Then you wouldn't need the extra
> alignment stuff.
It would waste 16K or so per CPU. I don't think the if is a problem.
> > +/*
> > + * Stack layout:
> > + * +16 pt_regs
> > + * +8 stack mask for ist or 0
>
> What does that mean?
>
> Oh, I get it. It's the size of the IST stack we're on. Let's please
> make all IST stacks the same size as suggested above and get rid of
> this. After all, they really are all the same size -- there's just
> more than one debug stack.
I don't want to waste the memory here. A few instructions more is much
preferable.
> > + movq_cfi rdx, RDX+OFF
> > + movq_cfi rcx, RCX+OFF
> > + movq_cfi rax, RAX+OFF
> > + movq %r8, R8+OFF(%rsp)
> > + movq %r9, R9+OFF(%rsp)
> > + movq %r10, R10+OFF(%rsp)
> > + movq %r11, R11+OFF(%rsp)
> > + movq_cfi rbx, RBX+OFF
> > + movq %rbp, RBP+OFF(%rsp)
> > + movq %r12, R12+OFF(%rsp)
> > + movq %r13, R13+OFF(%rsp)
> > + movq %r14, R14+OFF(%rsp)
> > + movq %r15, R15+OFF(%rsp)
> > + movq $-1,ORIG_RAX+OFF(%rsp) /* no syscall to restart */
> > +33:
> > + ASM_NOP5 /* May be replaced with jump to paranoid_save_gs */
>
> Is there some reason that the normal ALTERNATIVE macro can't be used here?
This is assembler, not C.
Since you asked for such extensive use I added a new macro for it now.
> > +.macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 \
> > + stack_mask=-EXCEPTION_STKSZ
>
> This can be removed as well, I think.
No with the different sized stacks.
-Andi
--
ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2015-04-10 20:21 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-10 15:50 Updated RD/WRFS/GSBASE patchkit Andi Kleen
2015-04-10 15:50 ` [PATCH 1/8] percpu: Add a DEFINE_PER_CPU_2PAGE_ALIGNED Andi Kleen
2015-04-10 15:50 ` [PATCH 2/8] x86: Naturally align the debug IST stack Andi Kleen
2015-04-10 18:50 ` Andy Lutomirski
2015-04-10 15:50 ` [PATCH 3/8] x86: Add intrinsics/macros for new rd/wr fs/gs base instructions Andi Kleen
2015-04-10 19:06 ` Andy Lutomirski
2015-04-10 19:07 ` Andy Lutomirski
2015-04-10 15:50 ` [PATCH 4/8] x86: Add support for rd/wr fs/gs base Andi Kleen
2015-04-10 19:12 ` Andy Lutomirski
2015-04-10 20:21 ` Andi Kleen [this message]
2015-04-10 20:25 ` Borislav Petkov
2015-04-10 20:52 ` Andi Kleen
2015-04-10 20:53 ` Borislav Petkov
2015-04-10 20:34 ` Andy Lutomirski
2015-04-10 20:41 ` Andi Kleen
2015-04-10 20:47 ` Andy Lutomirski
2015-04-10 20:57 ` Andi Kleen
2015-04-10 21:07 ` Andy Lutomirski
2015-04-10 22:52 ` Andi Kleen
2015-04-10 23:00 ` Andy Lutomirski
2015-04-10 23:05 ` Andi Kleen
2015-04-10 23:15 ` Andy Lutomirski
2015-04-10 23:18 ` Andi Kleen
2015-04-10 23:21 ` Andy Lutomirski
2015-04-10 23:16 ` Andi Kleen
2015-04-13 7:07 ` Jan Beulich
2015-04-10 15:50 ` [PATCH 5/8] x86: Make old K8 swapgs workaround conditional Andi Kleen
2015-04-10 21:46 ` Andy Lutomirski
2015-04-10 22:01 ` Borislav Petkov
2015-04-10 23:10 ` Andi Kleen
2015-04-11 7:18 ` Borislav Petkov
2015-04-10 15:50 ` [PATCH 6/8] x86: Enumerate kernel FSGS capability in AT_HWCAP2 Andi Kleen
2015-04-10 19:15 ` Andy Lutomirski
2015-04-10 22:14 ` Borislav Petkov
2015-04-10 23:07 ` Andi Kleen
2015-04-10 23:08 ` Andi Kleen
2015-04-11 7:16 ` Borislav Petkov
2015-04-11 8:35 ` Intel FSGSBASE support (was: Re: [PATCH 6/8] x86: Enumerate kernel FSGS capability in AT_HWCAP2) Ingo Molnar
2015-04-10 15:50 ` [PATCH 7/8] x86: Add documentation for rd/wr fs/gs base Andi Kleen
2015-04-10 19:17 ` Andy Lutomirski
2015-04-10 20:22 ` Andi Kleen
2015-04-10 20:38 ` Andy Lutomirski
2015-04-10 20:46 ` Andi Kleen
2015-04-10 20:52 ` Andy Lutomirski
2015-04-10 15:50 ` [PATCH 8/8] x86: Use rd/wr fs/gs base in arch_prctl Andi Kleen
2015-04-10 19:19 ` Andy Lutomirski
2015-04-10 19:58 ` Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2014-11-10 23:55 [PATCH 1/8] percpu: Add a DEFINE_PER_CPU_2PAGE_ALIGNED Andi Kleen
2014-11-10 23:55 ` [PATCH 4/8] x86: Add support for rd/wr fs/gs base Andi Kleen
2014-11-11 20:05 ` Andy Lutomirski
2014-11-11 20:49 ` Andy Lutomirski
2014-10-15 5:11 [PATCH 1/8] percpu: Add a DEFINE_PER_CPU_2PAGE_ALIGNED Andi Kleen
2014-10-15 5:11 ` [PATCH 4/8] x86: Add support for rd/wr fs/gs base Andi Kleen
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