From: Andi Kleen <andi@firstfloor.org>
To: peterz@infradead.org
Cc: acme@kernel.org, linux-kernel@vger.kernel.org, jolsa@redhat.com,
eranian@google.com, Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 5/5] x86, perf: Limit LBR accesses to TOS in callstack mode
Date: Wed, 27 May 2015 21:13:18 -0700 [thread overview]
Message-ID: <1432786398-23861-6-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1432786398-23861-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
In callstack mode the LBR is not a ring buffer, but a stack that grows up
and down. This means in this case we don't need to access all LBRs, only the
ones up to TOS. Do this optimization for the normal LBR read, and the context
switch save/restore code. For save/restore it can be done unconditionally, as
it only runs when call stack mode is active.
This recovers some of the cost of going to 32 LBRs on Skylake.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel_lbr.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index fa5c731..8e1740e 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -238,7 +238,7 @@ static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx)
mask = x86_pmu.lbr_nr - 1;
tos = intel_pmu_lbr_tos();
- for (i = 0; i < x86_pmu.lbr_nr; i++) {
+ for (i = 0; i < tos; i++) {
lbr_idx = (tos - i) & mask;
wrmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]);
wrmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]);
@@ -261,7 +261,7 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
mask = x86_pmu.lbr_nr - 1;
tos = intel_pmu_lbr_tos();
- for (i = 0; i < x86_pmu.lbr_nr; i++) {
+ for (i = 0; i < tos; i++) {
lbr_idx = (tos - i) & mask;
rdmsrl(x86_pmu.lbr_from + lbr_idx, task_ctx->lbr_from[i]);
rdmsrl(x86_pmu.lbr_to + lbr_idx, task_ctx->lbr_to[i]);
@@ -436,8 +436,12 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc,
u64 tos = intel_pmu_lbr_tos();
int i;
int out = 0;
+ int num = x86_pmu.lbr_nr;
- for (i = 0; i < x86_pmu.lbr_nr; i++) {
+ if (cpuc->lbr_sel->config & LBR_CALL_STACK)
+ num = tos;
+
+ for (i = 0; i < num; i++) {
unsigned long lbr_idx = (tos - i) & mask;
u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
int skip = 0;
--
2.1.0
next prev parent reply other threads:[~2015-05-28 4:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-28 4:13 Andi Kleen
2015-05-28 4:13 ` [PATCH 1/5] x86, perf: Allow time stamp for free running PEBSv3 Andi Kleen
2015-08-04 8:56 ` [tip:perf/core] perf/x86/intel/lbr: " tip-bot for Andi Kleen
2015-05-28 4:13 ` [PATCH 2/5] x86, perf: Add option to disable reading branch flags/cycles Andi Kleen
2015-06-15 10:48 ` Peter Zijlstra
2015-05-28 4:13 ` [PATCH 3/5] perf, tools: Disable branch flags/cycles for lbr call graph Andi Kleen
2015-05-28 4:13 ` [PATCH 4/5] x86, perf: Use correct index to save/restore LBR_INFO with callstack Andi Kleen
2015-08-04 8:59 ` [tip:perf/core] perf/x86/intel/lbr: Use correct index to save/ restore LBR_INFO with call stack tip-bot for Andi Kleen
2015-05-28 4:13 ` Andi Kleen [this message]
2015-08-04 8:59 ` [tip:perf/core] perf/x86/intel/lbr: Limit LBR accesses to TOS in callstack mode tip-bot for Andi Kleen
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