[PATCH 0/3] Imagination Technologies MIPS M6250 CPU support

[PATCH 0/3] Imagination Technologies MIPS M6250 CPU support

[Paul Burton]

This series adds support for probing the Imagination Technologies MIPS
M6250 CPU. This is a small, low power microprocessor implementing the
MIPS32r6 architecture. We already support everything required for it to
work, so this series simply adds the PRID & various switch cases then
matches the PRID during probe.

This applies atop v4.5-rc2 with the similar P6600 patch set applied
first. There is no real dependency between the two patch sets, just
overlap in the context of the changes.

Paul Burton (3):
  MIPS: Add M6250 PRID & cpu_type_enum values
  MIPS: Add M6250 cases to CPU switch statements
  MIPS: Probe the M6250 CPU

 arch/mips/include/asm/cpu-type.h | 4 ++++
 arch/mips/include/asm/cpu.h      | 3 ++-
 arch/mips/kernel/cpu-probe.c     | 4 ++++
 arch/mips/mm/c-r4k.c             | 1 +
 4 files changed, 11 insertions(+), 1 deletion(-)

-- 
2.7.0

[PATCH 1/3] MIPS: Add M6250 PRID & cpu_type_enum values

[Paul Burton]

Define the processor ID for the M6250 CPU and add a value to the enum
cpu_type_enum for the core.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/include/asm/cpu.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 7908dc2..96b7dd1 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -122,6 +122,7 @@
 #define PRID_IMP_M5150		0xa700
 #define PRID_IMP_P5600		0xa800
 #define PRID_IMP_I6400		0xa900
+#define PRID_IMP_M6250		0xab00
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -309,7 +310,7 @@ enum cpu_type_enum {
 	CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
 	CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
 	CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, CPU_M5150,
-	CPU_I6400, CPU_P6600,
+	CPU_I6400, CPU_P6600, CPU_M6250,
 
 	/*
 	 * MIPS64 class processors
-- 
2.7.0

[PATCH 2/3] MIPS: Add M6250 cases to CPU switch statements

[Paul Burton]

Add casses supporting the M6250 CPU to various switch statements in the
core MIPS kernel code that define behaviour dependent upon the CPU.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 arch/mips/include/asm/cpu-type.h | 4 ++++
 arch/mips/mm/c-r4k.c             | 1 +
 2 files changed, 5 insertions(+)

diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 2cb0979..fbe1881 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -77,6 +77,10 @@ static inline int __pure __get_cpu_type(const int cpu_type)
 	 */
 #endif
 
+#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R6
+	case CPU_M6250:
+#endif
+
 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6
 	case CPU_I6400:
 	case CPU_P6600:
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 2f47999..141161a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1279,6 +1279,7 @@ static void probe_pcache(void)
 	case CPU_QEMU_GENERIC:
 	case CPU_I6400:
 	case CPU_P6600:
+	case CPU_M6250:
 		if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
 		    (c->icache.waysize > PAGE_SIZE))
 			c->icache.flags |= MIPS_CACHE_ALIASES;
-- 
2.7.0

[PATCH 3/3] MIPS: Probe the M6250 CPU

[Paul Burton]

Support probing the M6250 CPU now that cases for handling it have been
added where required in the core MIPS kernel code.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

---

 arch/mips/kernel/cpu-probe.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 92cc4d8..429e2e1 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1327,6 +1327,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 		c->cputype = CPU_M5150;
 		__cpu_name[cpu] = "MIPS M5150";
 		break;
+	case PRID_IMP_M6250:
+		c->cputype = CPU_M6250;
+		__cpu_name[cpu] = "MIPS M6250";
+		break;
 	}
 
 	decode_configs(c);
-- 
2.7.0