From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
To: <bp@alien8.de>, <tony.luck@intel.com>, <hpa@zytor.com>,
<mingo@redhat.com>, <tglx@linutronix.de>,
<dougthompson@xmission.com>, <mchehab@osg.samsung.com>
Cc: <x86@kernel.org>, <linux-edac@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <ashok.raj@intel.com>,
<gong.chen@linux.intel.com>, <len.brown@intel.com>,
<peterz@infradead.org>, <ak@linux.intel.com>,
<alexander.shishkin@linux.intel.com>
Subject: [PATCH V2 5/5] x86/mce/AMD: Add comments for easier understanding
Date: Mon, 29 Feb 2016 16:32:59 -0600 [thread overview]
Message-ID: <1456785179-14378-6-git-send-email-Aravind.Gopalakrishnan@amd.com> (raw)
In-Reply-To: <1456785179-14378-1-git-send-email-Aravind.Gopalakrishnan@amd.com>
In an attempt to aid in understand of what threshold_block
structure holds, assing comments to describe the members here.
Also, trimming comments around threshold_restart_bank()
and updating copyright info.
No functional change is introduced.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
arch/x86/include/asm/amd_nb.h | 18 +++++++++---------
arch/x86/kernel/cpu/mcheck/mce_amd.c | 7 ++-----
2 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 3c56ef1..bc01c0a 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -27,15 +27,15 @@ struct amd_l3_cache {
};
struct threshold_block {
- unsigned int block;
- unsigned int bank;
- unsigned int cpu;
- u32 address;
- u16 interrupt_enable;
- bool interrupt_capable;
- u16 threshold_limit;
- struct kobject kobj;
- struct list_head miscj;
+ unsigned int block; /* Threshold block number within bank */
+ unsigned int bank; /* MCA bank the block belongs to */
+ unsigned int cpu; /* CPU which controls the MCA bank */
+ u32 address; /* MSR address for the block */
+ u16 interrupt_enable; /* Enable/ Disable APIC interrupt upon threshold error */
+ bool interrupt_capable; /* Specifies if interrupt is possible from the block */
+ u16 threshold_limit; /* Value upon which threshold interrupt is generated */
+ struct kobject kobj; /* sysfs object */
+ struct list_head miscj; /* Add multiple threshold blocks within a bank to the list */
};
struct threshold_bank {
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index a155eaa..ebb63ec 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -1,5 +1,5 @@
/*
- * (c) 2005-2015 Advanced Micro Devices, Inc.
+ * (c) 2005-2016 Advanced Micro Devices, Inc.
* Your use of this code is subject to the terms and conditions of the
* GNU general public license version 2. See "COPYING" or
* http://www.gnu.org/licenses/gpl.html
@@ -183,10 +183,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
return 1;
};
-/*
- * Called via smp_call_function_single(), must be called with correct
- * cpu affinity.
- */
+/* Reprogram MCx_MISC MSR behind this threshold bank */
static void threshold_restart_bank(void *_tr)
{
struct thresh_restart *tr = _tr;
--
2.7.0
prev parent reply other threads:[~2016-02-29 22:17 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-29 22:32 [PATCH V2 0/5] Updates to EDAC and AMD MCE driver Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 1/5] x86/mce: Move MCx_CONFIG MSR definition Aravind Gopalakrishnan
2016-03-08 13:12 ` [tip:ras/core] x86/mce: Move MCx_CONFIG MSR definitions tip-bot for Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors Aravind Gopalakrishnan
2016-03-02 10:50 ` Borislav Petkov
2016-03-02 10:52 ` [PATCH 1/3] x86/mce/AMD, EDAC: " Borislav Petkov
2016-03-02 10:53 ` [PATCH 2/3] x86/mce/AMD, EDAC: Simplify SMCA decoding Borislav Petkov
2016-03-02 15:52 ` Aravind Gopalakrishnan
2016-03-02 16:21 ` Borislav Petkov
2016-03-02 16:27 ` Aravind Gopalakrishnan
2016-03-02 16:38 ` Borislav Petkov
2016-03-02 16:54 ` Aravind Gopalakrishnan
2016-03-02 10:54 ` [PATCH 3/3] EDAC, mce_amd: Correct error paths Borislav Petkov
2016-03-02 15:56 ` Aravind Gopalakrishnan
2016-03-02 15:57 ` [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 3/5] x86/mce/AMD: Fix logic to obtain block address Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 4/5] x86/mce: Clarify comments regarding deferred error Aravind Gopalakrishnan
2016-02-29 22:32 ` Aravind Gopalakrishnan [this message]
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