From: Borislav Petkov <bp@alien8.de>
To: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Cc: tony.luck@intel.com, hpa@zytor.com, mingo@redhat.com,
tglx@linutronix.de, dougthompson@xmission.com,
mchehab@osg.samsung.com, x86@kernel.org,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
ashok.raj@intel.com, gong.chen@linux.intel.com,
len.brown@intel.com, peterz@infradead.org, ak@linux.intel.com,
alexander.shishkin@linux.intel.com
Subject: Re: [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
Date: Wed, 2 Mar 2016 11:50:32 +0100 [thread overview]
Message-ID: <20160302105032.GC16954@pd.tnic> (raw)
In-Reply-To: <1456785179-14378-3-git-send-email-Aravind.Gopalakrishnan@amd.com>
On Mon, Feb 29, 2016 at 04:32:56PM -0600, Aravind Gopalakrishnan wrote:
> For Scalable MCA enabled processors, errors are listed
> per IP block. And since it is not required for an IP to
> map to a particular bank, we need to use HWID and McaType
> values from the MCx_IPID register to figure out which IP
> a given bank represents.
>
> We also have a new bit (TCC) in the MCx_STATUS register
> to indicate Task context is corrupt.
>
> Add logic here to decode errors from all known IP
> blocks for Fam17h Model 00-0fh and to print TCC errors.
>
> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
> ---
> arch/x86/include/asm/mce.h | 53 ++++++
> arch/x86/kernel/cpu/mcheck/mce_amd.c | 11 ++
> drivers/edac/mce_amd.c | 342 ++++++++++++++++++++++++++++++++++-
> 3 files changed, 405 insertions(+), 1 deletion(-)
Ok, applied with a bunch of changes ontop. I'm sending them as a reply
to this message. The second patch is relying on the assumption that a
hwid of 0 is invalid. Is that so?
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
next prev parent reply other threads:[~2016-03-02 10:50 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-29 22:32 [PATCH V2 0/5] Updates to EDAC and AMD MCE driver Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 1/5] x86/mce: Move MCx_CONFIG MSR definition Aravind Gopalakrishnan
2016-03-08 13:12 ` [tip:ras/core] x86/mce: Move MCx_CONFIG MSR definitions tip-bot for Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors Aravind Gopalakrishnan
2016-03-02 10:50 ` Borislav Petkov [this message]
2016-03-02 10:52 ` [PATCH 1/3] x86/mce/AMD, EDAC: " Borislav Petkov
2016-03-02 10:53 ` [PATCH 2/3] x86/mce/AMD, EDAC: Simplify SMCA decoding Borislav Petkov
2016-03-02 15:52 ` Aravind Gopalakrishnan
2016-03-02 16:21 ` Borislav Petkov
2016-03-02 16:27 ` Aravind Gopalakrishnan
2016-03-02 16:38 ` Borislav Petkov
2016-03-02 16:54 ` Aravind Gopalakrishnan
2016-03-02 10:54 ` [PATCH 3/3] EDAC, mce_amd: Correct error paths Borislav Petkov
2016-03-02 15:56 ` Aravind Gopalakrishnan
2016-03-02 15:57 ` [PATCH V2 2/5] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 3/5] x86/mce/AMD: Fix logic to obtain block address Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 4/5] x86/mce: Clarify comments regarding deferred error Aravind Gopalakrishnan
2016-02-29 22:32 ` [PATCH V2 5/5] x86/mce/AMD: Add comments for easier understanding Aravind Gopalakrishnan
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