From: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org
Cc: bp@suse.de, dave.hansen@linux.intel.com,
linux-kernel@vger.kernel.org, lukasz.daniluk@intel.com,
james.h.cownie@intel.com,
Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Subject: [PATCH v1 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing
Date: Wed, 12 Oct 2016 12:13:06 +0200 [thread overview]
Message-ID: <1476267190-2303-1-git-send-email-grzegorz.andrejczuk@intel.com> (raw)
These patches enable Intel Xeon Phi x200 feature to use MONITOR/MWAIT
instruction in ring 3 (userspace) Patches set MSR 0x140 for all logical CPUs.
Then expose it as CPU feature and introduces elf HWCAP capability for x86.
Reference:
https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait
Grzegorz Andrejczuk (4):
Add R3MWAIT register and bit to msr-info.h
Add enabling of the R3 MWAIT during boot for KNL
Add hwcap2 for x86
Add R3MWAIT to CPU features
arch/x86/include/asm/cpufeature.h | 6 ++++--
arch/x86/include/asm/cpufeatures.h | 6 +++++-
arch/x86/include/asm/disabled-features.h | 3 ++-
arch/x86/include/asm/elf.h | 7 +++++++
arch/x86/include/asm/msr-index.h | 5 +++++
arch/x86/include/asm/required-features.h | 3 ++-
arch/x86/include/uapi/asm/hwcap.h | 7 +++++++
arch/x86/kernel/cpu/common.c | 6 ++++++
arch/x86/kernel/cpu/intel.c | 27 +++++++++++++++++++++++++++
9 files changed, 65 insertions(+), 5 deletions(-)
create mode 100644 arch/x86/include/uapi/asm/hwcap.h
--
2.5.1
next reply other threads:[~2016-10-12 10:13 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-12 10:13 Grzegorz Andrejczuk [this message]
2016-10-12 10:13 ` [PATCH v1 1/4] Add R3MWAIT register and bit to msr-info.h Grzegorz Andrejczuk
2016-10-12 10:13 ` [PATCH v1 2/4] Add enabling of the R3 MWAIT during boot for KNL Grzegorz Andrejczuk
2016-10-12 10:36 ` Borislav Petkov
2016-10-12 10:13 ` [PATCH v1 3/4] Add hwcap2 for x86 Grzegorz Andrejczuk
2016-10-12 10:23 ` [PATCH " Grzegorz Andrejczuk
2016-10-12 10:13 ` [PATCH v1 4/4] Add R3MWAIT to CPU features Grzegorz Andrejczuk
2016-10-12 10:32 ` Borislav Petkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1476267190-2303-1-git-send-email-grzegorz.andrejczuk@intel.com \
--to=grzegorz.andrejczuk@intel.com \
--cc=bp@suse.de \
--cc=dave.hansen@linux.intel.com \
--cc=hpa@zytor.com \
--cc=james.h.cownie@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=lukasz.daniluk@intel.com \
--cc=mingo@redhat.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®