From: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
To: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org
Cc: bp@suse.de, dave.hansen@linux.intel.com,
linux-kernel@vger.kernel.org, lukasz.daniluk@intel.com,
james.h.cownie@intel.com,
Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Subject: [PATCH v1 4/4] Add R3MWAIT to CPU features
Date: Wed, 12 Oct 2016 12:13:10 +0200 [thread overview]
Message-ID: <1476267190-2303-5-git-send-email-grzegorz.andrejczuk@intel.com> (raw)
In-Reply-To: <1476267190-2303-1-git-send-email-grzegorz.andrejczuk@intel.com>
Add cpu feature for ring 3 monitor/mwait.
Change-Id: Iba4d20639efd8d3637d37db9294cbc43a98f009a
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
arch/x86/include/asm/cpufeature.h | 6 ++++--
arch/x86/include/asm/cpufeatures.h | 6 +++++-
arch/x86/include/asm/disabled-features.h | 3 ++-
arch/x86/include/asm/required-features.h | 3 ++-
arch/x86/kernel/cpu/common.c | 3 +++
arch/x86/kernel/cpu/intel.c | 1 +
6 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 1d2b69f..1baa1df 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -78,8 +78,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
+ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
REQUIRED_MASK_CHECK || \
- BUILD_BUG_ON_ZERO(NCAPINTS != 18))
+ BUILD_BUG_ON_ZERO(NCAPINTS != 19))
#define DISABLED_MASK_BIT_SET(feature_bit) \
( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
@@ -100,8 +101,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
+ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
DISABLED_MASK_CHECK || \
- BUILD_BUG_ON_ZERO(NCAPINTS != 18))
+ BUILD_BUG_ON_ZERO(NCAPINTS != 19))
#define cpu_has(c, bit) \
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 92a8308..242cd16 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -12,7 +12,7 @@
/*
* Defines x86 CPU feature bits
*/
-#define NCAPINTS 18 /* N 32-bit words worth of info */
+#define NCAPINTS 19 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -286,6 +286,10 @@
#define X86_FEATURE_SUCCOR (17*32+1) /* Uncorrectable error containment and recovery */
#define X86_FEATURE_SMCA (17*32+3) /* Scalable MCA */
+
+/* non architectural Intel-defined CPU features not present in CPUID, word 18 */
+#define X86_FEATURE_PHIR3MWAIT (18*32+ 0)
+
/*
* BUG word(s)
*/
diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
index 85599ad..8b45e08 100644
--- a/arch/x86/include/asm/disabled-features.h
+++ b/arch/x86/include/asm/disabled-features.h
@@ -57,6 +57,7 @@
#define DISABLED_MASK15 0
#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE)
#define DISABLED_MASK17 0
-#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
+#define DISABLED_MASK18 0
+#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
#endif /* _ASM_X86_DISABLED_FEATURES_H */
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index fac9a5c..6847d85 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -100,6 +100,7 @@
#define REQUIRED_MASK15 0
#define REQUIRED_MASK16 0
#define REQUIRED_MASK17 0
-#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
+#define REQUIRED_MASK18 0
+#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)
#endif /* _ASM_X86_REQUIRED_FEATURES_H */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 93ffaa5..15fe27f 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1108,6 +1108,9 @@ static void identify_cpu(struct cpuinfo_x86 *c)
#endif
/* The boot/hotplug time assigment got cleared, restore it */
c->logical_proc_id = topology_phys_to_logical_pkg(c->phys_proc_id);
+
+ if (cpu_has(c, X86_FEATURE_PHIR3MWAIT))
+ elf_hwcap2 |= HWCAP2_PHIR3MWAIT;
}
/*
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7f0f01a..1f65815 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -236,6 +236,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
rdmsrl(MSR_PHI_MISC_THD_FEATURE_ENABLE, prev);
wrmsrl(MSR_PHI_MISC_THD_FEATURE_ENABLE,
prev | MSR_PHI_MISC_THD_FEATURE_ENABLE_R3MWAIT);
+ set_cpu_cap(c, X86_FEATURE_PHIR3MWAIT);
}
}
--
2.5.1
next prev parent reply other threads:[~2016-10-12 10:14 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-12 10:13 [PATCH v1 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
2016-10-12 10:13 ` [PATCH v1 1/4] Add R3MWAIT register and bit to msr-info.h Grzegorz Andrejczuk
2016-10-12 10:13 ` [PATCH v1 2/4] Add enabling of the R3 MWAIT during boot for KNL Grzegorz Andrejczuk
2016-10-12 10:36 ` Borislav Petkov
2016-10-12 10:13 ` [PATCH v1 3/4] Add hwcap2 for x86 Grzegorz Andrejczuk
2016-10-12 10:23 ` [PATCH " Grzegorz Andrejczuk
2016-10-12 10:13 ` Grzegorz Andrejczuk [this message]
2016-10-12 10:32 ` [PATCH v1 4/4] Add R3MWAIT to CPU features Borislav Petkov
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