From: "Fenghua Yu" <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>
Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
"Ingo Molnar" <mingo@elte.hu>, "Tony Luck" <tony.luck@intel.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Stephane Eranian" <eranian@google.com>,
"Borislav Petkov" <bp@suse.de>,
"Dave Hansen" <dave.hansen@intel.com>,
"Nilay Vaish" <nilayvaish@gmail.com>, "Shaohua Li" <shli@fb.com>,
"David Carrillo-Cisneros" <davidcc@google.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>,
"Sai Prakhya" <sai.praneeth.prakhya@intel.com>,
"Vikas Shivappa" <vikas.shivappa@linux.intel.com>,
"linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>, "Fenghua Yu" <fenghua.yu@intel.com>
Subject: [PATCH v5 01/18] Documentation, ABI: Add a document entry for cache id
Date: Sat, 22 Oct 2016 06:19:48 -0700 [thread overview]
Message-ID: <1477142405-32078-2-git-send-email-fenghua.yu@intel.com> (raw)
In-Reply-To: <1477142405-32078-1-git-send-email-fenghua.yu@intel.com>
From: Tony Luck <tony.luck@intel.com>
Add an ABI document entry for /sys/devices/system/cpu/cpu*/cache/index*/id.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
---
Documentation/ABI/testing/sysfs-devices-system-cpu | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
index 4987417..2a4a423 100644
--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
@@ -272,6 +272,22 @@ Description: Parameters for the CPU cache attributes
the modified cache line is written to main
memory only when it is replaced
+
+What: /sys/devices/system/cpu/cpu*/cache/index*/id
+Date: September 2016
+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
+Description: Cache id
+
+ The id provides a unique number for a specific instance of
+ a cache of a particular type. E.g. there may be a level
+ 3 unified cache on each socket in a server and we may
+ assign them ids 0, 1, 2, ...
+
+ Note that id value can be non-contiguous. E.g. level 1
+ caches typically exist per core, but there may not be a
+ power of two cores on a socket, so these caches may be
+ numbered 0, 1, 2, 3, 4, 5, 8, 9, 10, ...
+
What: /sys/devices/system/cpu/cpuX/cpufreq/throttle_stats
/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/turbo_stat
/sys/devices/system/cpu/cpuX/cpufreq/throttle_stats/sub_turbo_stat
--
2.5.0
next prev parent reply other threads:[~2016-10-22 13:23 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-22 13:19 [PATCH v5 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-22 13:19 ` Fenghua Yu [this message]
2016-10-26 21:25 ` [tip:x86/cache] Documentation, ABI: Document the new sysfs files for cpu cache ids tip-bot for Tony Luck
2016-10-22 13:19 ` [PATCH v5 02/18] cacheinfo: Introduce cache id Fenghua Yu
2016-10-26 21:25 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 03/18] x86/intel_cacheinfo: Enable cache id in cache info Fenghua Yu
2016-10-26 21:26 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-26 14:15 ` Borislav Petkov
2016-10-26 14:28 ` Thomas Gleixner
2016-10-26 21:26 ` [tip:x86/cache] x86/cpufeature: Add RDT CPUID feature bits tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-26 20:43 ` Thomas Gleixner
2016-10-26 21:27 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-26 21:27 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu
2016-10-26 21:28 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-26 21:29 ` [tip:x86/cache] x86/cqm: Share PQR_ASSOC related data between " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-26 13:02 ` Thomas Gleixner
2016-10-26 16:06 ` Luck, Tony
2016-10-26 17:31 ` Thomas Gleixner
2016-10-26 21:14 ` Fenghua Yu
2016-10-26 21:18 ` Thomas Gleixner
2016-10-22 13:19 ` [PATCH v5 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-26 13:52 ` Thomas Gleixner
2016-10-22 13:19 ` [PATCH v5 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-26 14:45 ` Thomas Gleixner
2016-10-26 15:48 ` Luck, Tony
2016-10-26 17:33 ` Thomas Gleixner
2016-10-27 18:17 ` Fenghua Yu
2016-10-27 18:25 ` Thomas Gleixner
2016-10-27 18:35 ` Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-26 15:01 ` Thomas Gleixner
2016-10-28 17:51 ` Fenghua Yu
2016-10-28 18:41 ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-26 17:57 ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-26 15:27 ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
2016-10-26 21:39 ` [PATCH v5 00/18] Intel Cache Allocation Technology Thomas Gleixner
2016-10-26 21:54 ` Fenghua Yu
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