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From: Thomas Gleixner <tglx@linutronix.de>
To: Fenghua Yu <fenghua.yu@intel.com>
Cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
	Ingo Molnar <mingo@elte.hu>, Tony Luck <tony.luck@intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Stephane Eranian <eranian@google.com>,
	Borislav Petkov <bp@suse.de>, Dave Hansen <dave.hansen@intel.com>,
	Nilay Vaish <nilayvaish@gmail.com>, Shaohua Li <shli@fb.com>,
	David Carrillo-Cisneros <davidcc@google.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	Sai Prakhya <sai.praneeth.prakhya@intel.com>,
	Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v5 13/18] x86/intel_rdt: Add mkdir to resctrl file system
Date: Wed, 26 Oct 2016 17:01:32 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.20.1610261557130.4983@nanos> (raw)
In-Reply-To: <1477142405-32078-14-git-send-email-fenghua.yu@intel.com>

On Sat, 22 Oct 2016, Fenghua Yu wrote:
> +/*
> + * Trivial allocator for CLOSIDs. Since h/w only supports a small number,
> + * we can keep a bitmap of free CLOSIDs in a single integer.
> + *
> + * Using a global CLOSID across all resources has some advantages and
> + * some drawbacks:
> + * + We can simply set "current->closid" to assign a task to a resource
> + *   group.
> + * + Context switch code can avoid extra memory references deciding which
> + *   CLOSID to load into the PQR_ASSOC MSR
> + * - We give up some options in configuring resource groups across multi-socket
> + *   systems.
> + * - Our choices on how to configure each resource become progressively more
> + *   limited as the number of resources grows.
> + */
> +static int closid_free_map;
> +
> +static void closid_init(void)
> +{
> +	struct rdt_resource *r;
> +	int rdt_max_closid;
> +
> +	/* Compute rdt_max_closid across all resources */
> +	rdt_max_closid = 0;
> +	for_each_enabled_rdt_resource(r)
> +		rdt_max_closid = max(rdt_max_closid, r->num_closid);

So you decided to silently ignore my objections against this approach. Fine
with me, but that does not solve the problem at all.

Once more:

On a system with L2 and L3 CAT it does not make any sense at all to expose
the closids which exceed the L2 space. Simply because using them wreckages
any L2 partitioning done in the valid L2 space.

If you really want to allow that, then:

   1) It must be a opt-in at mount time

   2) It must be documented clearly along with the mount option

> +	/*
> +	 * CDP is "special". Because we share the L3 CBM MSR array
> +	 * between L3DATA and L3CODE, we must not use a CLOSID larger
> +	 * than they support. Just check against L3DATA because it
> +	 * is the same as L3CODE.
> +	 */
> +	r = &rdt_resources_all[RDT_RESOURCE_L3DATA];
> +	if (r->enabled)
> +		rdt_max_closid = min(rdt_max_closid, r->num_closid);

This explicit special casing is crap, really.

	for_each_enabled_rdt_resource(r)
		rdt_max_closid = max(rdt_max_closid, r->num_closid);

	for_each_enabled_rdt_resource(r) {
		if (!relaxed_max_closid || r->force_min_closid)
			rdt_max_closid = min(rdt_max_closid, r->num_closid);
	}

Handles all cases without 'CDP is special' and whatever nonsense intel will
come up with in future. All you need to do is to add that force_min_closid
field into the resource struct and set it for l3data and l3code.

relaxed_max_closid is set at mount time by an appropriate mount option.

Thanks,

	tglx

  reply	other threads:[~2016-10-26 15:04 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-22 13:19 [PATCH v5 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-26 21:25   ` [tip:x86/cache] Documentation, ABI: Document the new sysfs files for cpu cache ids tip-bot for Tony Luck
2016-10-22 13:19 ` [PATCH v5 02/18] cacheinfo: Introduce cache id Fenghua Yu
2016-10-26 21:25   ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 03/18] x86/intel_cacheinfo: Enable cache id in cache info Fenghua Yu
2016-10-26 21:26   ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-26 14:15   ` Borislav Petkov
2016-10-26 14:28     ` Thomas Gleixner
2016-10-26 21:26   ` [tip:x86/cache] x86/cpufeature: Add RDT CPUID feature bits tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-26 20:43   ` Thomas Gleixner
2016-10-26 21:27   ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-26 21:27   ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu
2016-10-26 21:28   ` [tip:x86/cache] " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-26 21:29   ` [tip:x86/cache] x86/cqm: Share PQR_ASSOC related data between " tip-bot for Fenghua Yu
2016-10-22 13:19 ` [PATCH v5 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-26 13:02   ` Thomas Gleixner
2016-10-26 16:06     ` Luck, Tony
2016-10-26 17:31       ` Thomas Gleixner
2016-10-26 21:14     ` Fenghua Yu
2016-10-26 21:18       ` Thomas Gleixner
2016-10-22 13:19 ` [PATCH v5 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-26 13:52   ` Thomas Gleixner
2016-10-22 13:19 ` [PATCH v5 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-26 14:45   ` Thomas Gleixner
2016-10-26 15:48     ` Luck, Tony
2016-10-26 17:33       ` Thomas Gleixner
2016-10-27 18:17     ` Fenghua Yu
2016-10-27 18:25       ` Thomas Gleixner
2016-10-27 18:35         ` Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-26 15:01   ` Thomas Gleixner [this message]
2016-10-28 17:51     ` Fenghua Yu
2016-10-28 18:41       ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-26 17:57   ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-26 15:27   ` Thomas Gleixner
2016-10-22 13:20 ` [PATCH v5 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-22 13:20 ` [PATCH v5 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu
2016-10-26 21:39 ` [PATCH v5 00/18] Intel Cache Allocation Technology Thomas Gleixner
2016-10-26 21:54   ` Fenghua Yu

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