Re: [PATCH 6/8] perf/x86/intel: Validate return value of intel_pmu_init_hybrid()

["Chen, Zide" <zide.chen@intel.com>]

On 6/4/2026 8:11 PM, Dapeng Mi wrote:
> The memory allocation for the x86_pmu.hybrid_pmu[] array in
> intel_pmu_init_hybrid() can theoretically fail due to memory shortages.
> If this occurs, the initialization of the x86 hybrid PMU would fail.
> 
> Currently, the code does not check the return value of the
> intel_pmu_init_hybrid() function, which could lead to attempts to access
> the uninitialized x86_pmu.hybrid_pmu[] array, potentially causing a
> system panic.
> 
> So, adds a check for the return value of intel_pmu_init_hybrid() to

typo: adds -> add.

> prevent invalid memory access in such scenarios. Besides, free the
> created kmem cache when error occurs.
> 
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> ---

Reviewed-by: Zide Chen <zide.chen@intel.com>


>  arch/x86/events/intel/core.c | 33 ++++++++++++++++++++++++++-------
>  1 file changed, 26 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index ea3ab3050a3b..efd9caa3502c 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -7870,6 +7870,7 @@ __init int intel_pmu_init(void)
>  	int version, i;
>  	char *name;
>  	struct x86_hybrid_pmu *pmu;
> +	int ret;
>  
>  	/* Architectural Perfmon was introduced starting with Core "Yonah" */
>  	if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
> @@ -8539,7 +8540,9 @@ __init int intel_pmu_init(void)
>  		 *
>  		 * Initialize the common PerfMon capabilities here.
>  		 */
> -		intel_pmu_init_hybrid(hybrid_big_small);
> +		ret = intel_pmu_init_hybrid(hybrid_big_small);
> +		if (ret < 0)
> +			goto err;
>  
>  		x86_pmu.pebs_latency_data = grt_latency_data;
>  		x86_pmu.get_event_constraints = adl_get_event_constraints;
> @@ -8597,7 +8600,9 @@ __init int intel_pmu_init(void)
>  	case INTEL_METEORLAKE:
>  	case INTEL_METEORLAKE_L:
>  	case INTEL_ARROWLAKE_U:
> -		intel_pmu_init_hybrid(hybrid_big_small);
> +		ret = intel_pmu_init_hybrid(hybrid_big_small);
> +		if (ret < 0)
> +			goto err;
>  
>  		x86_pmu.pebs_latency_data = cmt_latency_data;
>  		x86_pmu.get_event_constraints = mtl_get_event_constraints;
> @@ -8628,7 +8633,9 @@ __init int intel_pmu_init(void)
>  		pr_cont("Pantherlake Hybrid events, ");
>  		name = "pantherlake_hybrid";
>  
> -		intel_pmu_init_hybrid(hybrid_big_small);
> +		ret = intel_pmu_init_hybrid(hybrid_big_small);
> +		if (ret < 0)
> +			goto err;
>  
>  		/* Initialize big core specific PerfMon capabilities.*/
>  		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
> @@ -8643,7 +8650,9 @@ __init int intel_pmu_init(void)
>  		pr_cont("Arrowlake Hybrid events, ");
>  		name = "arrowlake_hybrid";
>  
> -		intel_pmu_init_hybrid(hybrid_big_small);
> +		ret = intel_pmu_init_hybrid(hybrid_big_small);
> +		if (ret < 0)
> +			goto err;
>  
>  		/* Initialize big core specific PerfMon capabilities.*/
>  		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
> @@ -8660,7 +8669,9 @@ __init int intel_pmu_init(void)
>  		pr_cont("Lunarlake Hybrid events, ");
>  		name = "lunarlake_hybrid";
>  
> -		intel_pmu_init_hybrid(hybrid_big_small);
> +		ret = intel_pmu_init_hybrid(hybrid_big_small);
> +		if (ret < 0)
> +			goto err;
>  
>  		/* Initialize big core specific PerfMon capabilities.*/
>  		pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
> @@ -8685,7 +8696,9 @@ __init int intel_pmu_init(void)
>  		break;
>  
>  	case INTEL_ARROWLAKE_H:
> -		intel_pmu_init_hybrid(hybrid_big_small_tiny);
> +		ret = intel_pmu_init_hybrid(hybrid_big_small_tiny);
> +		if (ret < 0)
> +			goto err;
>  
>  		x86_pmu.pebs_latency_data = arl_h_latency_data;
>  		x86_pmu.get_event_constraints = arl_h_get_event_constraints;
> @@ -8720,7 +8733,9 @@ __init int intel_pmu_init(void)
>  	case INTEL_NOVALAKE_L:
>  		pr_cont("Novalake Hybrid events, ");
>  		name = "novalake_hybrid";
> -		intel_pmu_init_hybrid(hybrid_big_small);
> +		ret = intel_pmu_init_hybrid(hybrid_big_small);
> +		if (ret < 0)
> +			goto err;
>  
>  		x86_pmu.pebs_latency_data = nvl_latency_data;
>  		x86_pmu.get_event_constraints = mtl_get_event_constraints;
> @@ -8885,6 +8900,10 @@ __init int intel_pmu_init(void)
>  	intel_aux_output_init();
>  
>  	return 0;
> +
> +err:
> +	kmem_cache_destroy(x86_get_pmu(smp_processor_id())->task_ctx_cache);
> +	return ret;
>  }
>  
>  /*