[RESEND PATCH v4 0/2] add thermal nodes for UniPhier SoCs

[RESEND PATCH v4 0/2] add thermal nodes for UniPhier SoCs

[Kunihiko Hayashi]

This series adds thermal nodes for UniPhier PXs2 and LD20 SoCs.

Resending the patches to apply the missing comments,
please ignore previous v4.

Changes since v3:
- use the dt-bindings header to replace the limit values with THERMAL_NO_LIMIT
- add the calibration value to uniphier-pxs2.dtsi
- move the calibration value to uniphier-ld20.dtsi

Changes since v2:
- add the calibration value to device tree for LD20 reference board

Changes since v1:
- separate from driver's patchset[1]
- add cooling-maps nodes on the device tree
- fix an interrupt trigger to set 'level-triggered' according to
  hardware specification
- bring up threshold temperature for LD20 according to the spec sheet
- add cpuN labels for reference in cooling-device property on PXs2 dts

[1] https://lkml.org/lkml/2017/6/28/170

Kunihiko Hayashi (2):
  ARM: dts: uniphier: add nodes of thermal monitor and thermal zone for
    PXs2
  arm64: dts: uniphier: add nodes of thermal monitor and thermal zone
    for LD20

 arch/arm/boot/dts/uniphier-pxs2.dtsi             | 47 ++++++++++++++++++++++--
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 45 +++++++++++++++++++++++
 2 files changed, 88 insertions(+), 4 deletions(-)

-- 
2.7.4

[RESEND PATCH v4 1/2] ARM: dts: uniphier: add nodes of thermal monitor and thermal zone for PXs2

[Kunihiko Hayashi]

Add nodes of thermal monitor and thermal zone for UniPhier PXs2 SoC.
The thermal monitor node is included in sysctrl. Since the efuse might not
have a calibrated value of thermal monitor, this patch gives the default
value for PXs2.

Furthermore, add cpuN labels for reference in cooling-device property.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 arch/arm/boot/dts/uniphier-pxs2.dtsi | 47 +++++++++++++++++++++++++++++++++---
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 90b020c..f2dfebe 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -7,6 +7,8 @@
  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
+#include <dt-bindings/thermal/thermal.h>
+
 / {
 	compatible = "socionext,uniphier-pxs2";
 	#address-cells = <1>;
@@ -16,7 +18,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
@@ -24,9 +26,10 @@
 			enable-method = "psci";
 			next-level-cache = <&l2>;
 			operating-points-v2 = <&cpu_opp>;
+			#cooling-cells = <2>;
 		};
 
-		cpu@1 {
+		cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
@@ -36,7 +39,7 @@
 			operating-points-v2 = <&cpu_opp>;
 		};
 
-		cpu@2 {
+		cpu2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <2>;
@@ -46,7 +49,7 @@
 			operating-points-v2 = <&cpu_opp>;
 		};
 
-		cpu@3 {
+		cpu3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <3>;
@@ -114,6 +117,35 @@
 		};
 	};
 
+	thermal-zones {
+		cpu_thermal {
+			polling-delay-passive = <250>;	/* 250ms */
+			polling-delay = <1000>;		/* 1000ms */
+			thermal-sensors = <&pvtctl>;
+
+			trips {
+				cpu_crit: cpu_crit {
+					temperature = <95000>;	/* 95C */
+					hysteresis = <2000>;
+					type = "critical";
+				};
+				cpu_alert: cpu_alert {
+					temperature = <85000>;	/* 85C */
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map {
+					trip = <&cpu_alert>;
+					cooling-device = <&cpu0
+					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -358,6 +390,13 @@
 				compatible = "socionext,uniphier-pxs2-reset";
 				#reset-cells = <1>;
 			};
+
+			pvtctl: pvtctl {
+				compatible = "socionext,uniphier-pxs2-thermal";
+				interrupts = <0 3 4>;
+				#thermal-sensor-cells = <0>;
+				socionext,tmod-calibration = <0x0f86 0x6844>;
+			};
 		};
 
 		nand: nand@68000000 {
-- 
2.7.4

[RESEND PATCH v4 2/2] arm64: dts: uniphier: add nodes of thermal monitor and thermal zone for LD20

[Kunihiko Hayashi]

Add nodes of thermal monitor and thermal zone for UniPhier LD20 SoC.
The thermal monitor node is included in sysctrl. Since the efuse might not
have a calibrated value of thermal monitor, this patch gives the default
value for LD20.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 45 ++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index a29c279..59e5ae6 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -7,6 +7,8 @@
  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  */
 
+#include <dt-bindings/thermal/thermal.h>
+
 /memreserve/ 0x80000000 0x02000000;
 
 / {
@@ -46,6 +48,7 @@
 			clocks = <&sys_clk 32>;
 			enable-method = "psci";
 			operating-points-v2 = <&cluster0_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu1: cpu@1 {
@@ -64,6 +67,7 @@
 			clocks = <&sys_clk 33>;
 			enable-method = "psci";
 			operating-points-v2 = <&cluster1_opp>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@101 {
@@ -173,6 +177,40 @@
 			     <1 10 4>;
 	};
 
+	thermal-zones {
+		cpu_thermal {
+			polling-delay-passive = <250>;	/* 250ms */
+			polling-delay = <1000>;		/* 1000ms */
+			thermal-sensors = <&pvtctl>;
+
+			trips {
+				cpu_crit: cpu_crit {
+					temperature = <110000>;	/* 110C */
+					hysteresis = <2000>;
+					type = "critical";
+				};
+				cpu_alert: cpu_alert {
+					temperature = <100000>;	/* 100C */
+					hysteresis = <2000>;
+					type = "passive";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device = <&cpu0
+					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu_alert>;
+					cooling-device = <&cpu2
+					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -410,6 +448,13 @@
 			watchdog {
 				compatible = "socionext,uniphier-wdt";
 			};
+
+			pvtctl: pvtctl {
+				compatible = "socionext,uniphier-ld20-thermal";
+				interrupts = <0 3 4>;
+				#thermal-sensor-cells = <0>;
+				socionext,tmod-calibration = <0x0f22 0x68ee>;
+			};
 		};
 
 		nand: nand@68000000 {
-- 
2.7.4

Re: [RESEND PATCH v4 0/2] add thermal nodes for UniPhier SoCs

[Masahiro Yamada]

2017-09-04 15:58 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> This series adds thermal nodes for UniPhier PXs2 and LD20 SoCs.
>
> Resending the patches to apply the missing comments,
> please ignore previous v4.
>
> Changes since v3:
> - use the dt-bindings header to replace the limit values with THERMAL_NO_LIMIT
> - add the calibration value to uniphier-pxs2.dtsi
> - move the calibration value to uniphier-ld20.dtsi
>
> Changes since v2:
> - add the calibration value to device tree for LD20 reference board
>
> Changes since v1:
> - separate from driver's patchset[1]
> - add cooling-maps nodes on the device tree
> - fix an interrupt trigger to set 'level-triggered' according to
>   hardware specification
> - bring up threshold temperature for LD20 according to the spec sheet
> - add cpuN labels for reference in cooling-device property on PXs2 dts
>
> [1] https://lkml.org/lkml/2017/6/28/170
>
> Kunihiko Hayashi (2):
>   ARM: dts: uniphier: add nodes of thermal monitor and thermal zone for
>     PXs2
>   arm64: dts: uniphier: add nodes of thermal monitor and thermal zone
>     for LD20
>
>  arch/arm/boot/dts/uniphier-pxs2.dtsi             | 47 ++++++++++++++++++++++--
>  arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 45 +++++++++++++++++++++++
>  2 files changed, 88 insertions(+), 4 deletions(-)
>

Series, applied to linux-uniphier.  Thanks!

-- 
Best Regards
Masahiro Yamada

Re: [RESEND PATCH v4 0/2] add thermal nodes for UniPhier SoCs

[Masahiro Yamada]

2017-09-18 21:10 GMT+09:00 Masahiro Yamada <yamada.masahiro@socionext.com>:
> 2017-09-04 15:58 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
>> This series adds thermal nodes for UniPhier PXs2 and LD20 SoCs.
>>
>> Resending the patches to apply the missing comments,
>> please ignore previous v4.
>>
>> Changes since v3:
>> - use the dt-bindings header to replace the limit values with THERMAL_NO_LIMIT
>> - add the calibration value to uniphier-pxs2.dtsi
>> - move the calibration value to uniphier-ld20.dtsi
>>
>> Changes since v2:
>> - add the calibration value to device tree for LD20 reference board
>>
>> Changes since v1:
>> - separate from driver's patchset[1]
>> - add cooling-maps nodes on the device tree
>> - fix an interrupt trigger to set 'level-triggered' according to
>>   hardware specification
>> - bring up threshold temperature for LD20 according to the spec sheet
>> - add cpuN labels for reference in cooling-device property on PXs2 dts
>>
>> [1] https://lkml.org/lkml/2017/6/28/170
>>
>> Kunihiko Hayashi (2):
>>   ARM: dts: uniphier: add nodes of thermal monitor and thermal zone for
>>     PXs2
>>   arm64: dts: uniphier: add nodes of thermal monitor and thermal zone
>>     for LD20
>>
>>  arch/arm/boot/dts/uniphier-pxs2.dtsi             | 47 ++++++++++++++++++++++--
>>  arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 45 +++++++++++++++++++++++
>>  2 files changed, 88 insertions(+), 4 deletions(-)
>>
>
> Series, applied to linux-uniphier.  Thanks!
>
> --
> Best Regards
> Masahiro Yamada


Both of the patches added W=2 warnings by '_' in the node names.

I fixed them up locally, per Rob's comment:
https://patchwork.kernel.org/patch/9988355/



-- 
Best Regards
Masahiro Yamada