From: Andrew Jeffery <andrew@aj.id.au>
To: Joel Stanley <joel@jms.id.au>
Cc: Lee Jones <lee.jones@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-clk@vger.kernel.org,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Jeremy Kerr <jk@ozlabs.org>, Rick Altherr <raltherr@google.com>,
Ryan Chen <ryan_chen@aspeedtech.com>,
Arnd Bergmann <arnd@arndb.de>
Subject: Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs
Date: Wed, 27 Sep 2017 17:04:05 +0930 [thread overview]
Message-ID: <1506497645.30138.37.camel@aj.id.au> (raw)
In-Reply-To: <CACPK8Xd8RQ4s1xMsSuxHgQRiHS6vDtxVTAxu8Ba3J3it45MC5g@mail.gmail.com>
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On Wed, 2017-09-27 at 16:13 +1000, Joel Stanley wrote:
> > > + div_table,
> >
> > This doesn't seem to be correct. There's the problem of 0b000 and 0b001 mapping
> > the same value of 2 for the AST2500, whose table then increments in steps of 1.
> > The AST2400 mapping on the otherhand is multiples of 2 starting at 2, with no
> > inconsistency for 0b000 vs 0b001.
>
> Yep, we do use a different table for ast2400 vs ast2500. See
> ast2400_div_table vs ast2500_div_table.
Yep, but for the AST2500 this is a different table again to what you've
already defined (for the AST2500). However, for the AST2400 the table
looks the same as the other AST2400 tables.
Cheers,
Andrew
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next prev parent reply other threads:[~2017-09-27 7:34 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-21 4:26 [PATCH v2 0/5] clk: Add Aspeed clock driver Joel Stanley
2017-09-21 4:26 ` [PATCH v2 1/5] clk: Add clock driver for ASPEED BMC SoCs Joel Stanley
2017-09-25 3:40 ` Andrew Jeffery
2017-09-27 6:11 ` Joel Stanley
2017-09-21 4:26 ` [PATCH v2 2/5] clk: aspeed: Register core clocks Joel Stanley
2017-09-25 12:02 ` Andrew Jeffery
2017-09-27 6:13 ` Joel Stanley
2017-10-02 21:39 ` Stephen Boyd
2017-09-21 4:26 ` [PATCH v2 3/5] clk: aspeed: Add platform driver and register PLLs Joel Stanley
2017-09-25 12:40 ` Andrew Jeffery
2017-09-27 6:13 ` Joel Stanley
2017-09-27 7:34 ` Andrew Jeffery [this message]
2017-09-28 4:29 ` Joel Stanley
2017-10-02 21:24 ` Stephen Boyd
2017-10-03 5:48 ` Joel Stanley
2017-10-04 21:18 ` Stephen Boyd
2017-10-05 6:22 ` Joel Stanley
2017-09-21 4:26 ` [PATCH v2 4/5] clk: aspeed: Register gated clocks Joel Stanley
2017-10-02 21:37 ` Stephen Boyd
2017-10-03 5:47 ` Joel Stanley
2017-09-21 4:26 ` [PATCH v2 5/5] clk: aspeed: Add reset controller Joel Stanley
2017-09-25 12:54 ` Andrew Jeffery
2017-09-27 6:13 ` Joel Stanley
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