From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com,
linux-kernel@vger.kernel.org, joro@8bytes.org,
Chao Peng <chao.p.peng@linux.intel.com>,
Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH V4 10/11] KVM: x86: Implement Intel Processor Trace MSRs read/write
Date: Mon, 11 Dec 2017 04:30:56 +0800 [thread overview]
Message-ID: <1512937857-10477-11-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1512937857-10477-1-git-send-email-luwei.kang@intel.com>
From: Chao Peng <chao.p.peng@linux.intel.com>
Intel PT MSRs read/write will not be intercepted when guest enabled
Intel PT. IA32_RTIT_CTL read/write will always cause a VM-Exit.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
arch/x86/kvm/vmx.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/x86/kvm/x86.c | 20 +++++++++++++++++
2 files changed, 84 insertions(+)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index d2e64bf..f948231 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -949,6 +949,7 @@ static void vmx_get_segment(struct kvm_vcpu *vcpu,
static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
u16 error_code);
static void pt_disable_intercept_for_msr(bool flag);
+static bool vmx_pt_supported(void);
static DEFINE_PER_CPU(struct vmcs *, vmxarea);
static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
@@ -3349,6 +3350,38 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
return 1;
msr_info->data = vcpu->arch.ia32_xss;
break;
+ case MSR_IA32_RTIT_CTL:
+ if (!vmx_pt_supported())
+ return 1;
+ msr_info->data = to_vmx(vcpu)->pt_desc.guest.ctl;
+ break;
+ case MSR_IA32_RTIT_STATUS:
+ if (!vmx_pt_supported())
+ return 1;
+ msr_info->data = to_vmx(vcpu)->pt_desc.guest.status;
+ break;
+ case MSR_IA32_RTIT_CR3_MATCH:
+ if (!vmx_pt_supported())
+ return 1;
+ msr_info->data = to_vmx(vcpu)->pt_desc.guest.cr3_match;
+ break;
+ case MSR_IA32_RTIT_OUTPUT_BASE:
+ if (!vmx_pt_supported())
+ return 1;
+ msr_info->data = to_vmx(vcpu)->pt_desc.guest.output_base;
+ break;
+ case MSR_IA32_RTIT_OUTPUT_MASK:
+ if (!vmx_pt_supported())
+ return 1;
+ msr_info->data = to_vmx(vcpu)->pt_desc.guest.output_mask;
+ break;
+ case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
+ if (!vmx_pt_supported())
+ return 1;
+ msr_info->data =
+ to_vmx(vcpu)->pt_desc.guest.addrs[msr_info->index -
+ MSR_IA32_RTIT_ADDR0_A];
+ break;
case MSR_TSC_AUX:
if (!msr_info->host_initiated &&
!guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
@@ -3473,6 +3506,37 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
else
clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
break;
+ case MSR_IA32_RTIT_CTL:
+ if (!vmx_pt_supported() || to_vmx(vcpu)->nested.vmxon)
+ return 1;
+ vmx_set_rtit_ctl(vcpu, data);
+ break;
+ case MSR_IA32_RTIT_STATUS:
+ if (!vmx_pt_supported())
+ return 1;
+ vmx->pt_desc.guest.status = data;
+ break;
+ case MSR_IA32_RTIT_CR3_MATCH:
+ if (!vmx_pt_supported())
+ return 1;
+ vmx->pt_desc.guest.cr3_match = data;
+ break;
+ case MSR_IA32_RTIT_OUTPUT_BASE:
+ if (!vmx_pt_supported())
+ return 1;
+ vmx->pt_desc.guest.output_base = data;
+ break;
+ case MSR_IA32_RTIT_OUTPUT_MASK:
+ if (!vmx_pt_supported())
+ return 1;
+ vmx->pt_desc.guest.output_mask = data;
+ break;
+ case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
+ if (!vmx_pt_supported())
+ return 1;
+ vmx->pt_desc.guest.addrs[msr_info->index -
+ MSR_IA32_RTIT_ADDR0_A] = data;
+ break;
case MSR_TSC_AUX:
if (!msr_info->host_initiated &&
!guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index b19a749..3f16626 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1022,6 +1022,12 @@ unsigned int kvm_get_pt_addr_cnt(void)
#endif
MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
+ MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
+ MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
+ MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
+ MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
+ MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
+ MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
};
static unsigned num_msrs_to_save;
@@ -4337,6 +4343,20 @@ static void kvm_init_msr_list(void)
if (!kvm_x86_ops->rdtscp_supported())
continue;
break;
+ case MSR_IA32_RTIT_CTL:
+ case MSR_IA32_RTIT_STATUS:
+ case MSR_IA32_RTIT_CR3_MATCH:
+ case MSR_IA32_RTIT_OUTPUT_BASE:
+ case MSR_IA32_RTIT_OUTPUT_MASK:
+ if (!kvm_x86_ops->pt_supported())
+ continue;
+ break;
+ case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
+ if (!kvm_x86_ops->pt_supported() || msrs_to_save[i] -
+ MSR_IA32_RTIT_ADDR0_A >= kvm_get_pt_addr_cnt())
+ continue;
+ break;
+ }
default:
break;
}
--
1.8.3.1
next prev parent reply other threads:[~2017-12-11 10:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-10 20:30 [PATCH V4 00/11] Intel Processor Trace virtulization enabling Luwei Kang
2017-12-10 20:30 ` [PATCH V4 01/11] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Luwei Kang
2017-12-10 20:30 ` [PATCH V4 02/11] perf/x86/intel/pt: Change pt_cap_get() to a public function Luwei Kang
2017-12-10 20:30 ` [PATCH V4 03/11] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2017-12-10 20:30 ` [PATCH V4 04/11] x86: cpufeature: move processor tracing out of scattered features Luwei Kang
2017-12-10 20:30 ` [PATCH V4 05/11] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2017-12-10 20:30 ` [PATCH V4 06/11] KVM: x86: Add a function to get the number of address ranges Luwei Kang
2017-12-10 20:30 ` [PATCH V4 07/11] KVM: x86: Add a function to disable/enable Intel PT MSRs intercept Luwei Kang
2017-12-10 20:30 ` [PATCH V4 08/11] KVM: x86: Add Intel processor trace context for each vcpu Luwei Kang
2017-12-10 20:30 ` [PATCH V4 09/11] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
[not found] ` <CALMp9eT63cMpJYBLP=9nSApP+=kwyht-XiDamHd6APfXr269Bg@mail.gmail.com>
2018-01-09 21:39 ` Paolo Bonzini
2017-12-10 20:30 ` Luwei Kang [this message]
2017-12-10 20:30 ` [PATCH V4 11/11] KVM: x86: Implement Intel Processor Trace context switch Luwei Kang
2017-12-12 17:06 ` Paolo Bonzini
2017-12-12 17:09 ` [PATCH V4 00/11] Intel Processor Trace virtulization enabling Paolo Bonzini
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