From: "Fenghua Yu" <fenghua.yu@intel.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@elte.hu>,
"H. Peter Anvin" <hpa@linux.intel.com>,
"Tony Luck" <tony.luck@intel.com>,
"Shivappa, Vikas" <vikas.shivappa@intel.com>,
"Ravi V Shankar" <ravi.v.shankar@intel.com>,
"Prakhya, Sai Praneeth" <sai.praneeth.prakhya@intel.com>,
"Chatre, Reinette" <reinette.chatre@intel.com>,
"linux-kernel" <linux-kernel@vger.kernel.org>,
"x86" <x86@kernel.org>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Subject: [PATCH 0/6] x86/intel_rdt: Enable L2 CDP (Code and Data Prioritization)
Date: Wed, 20 Dec 2017 14:57:18 -0800 [thread overview]
Message-ID: <1513810644-78015-1-git-send-email-fenghua.yu@intel.com> (raw)
From: Fenghua Yu <fenghua.yu@intel.com>
L2 CDP enables isolation and prioritization of code and data individually
within the L2 cache. The feature is enumerated in
CPUID.(EAX=0x10, ECX=2):ECX.CDP[bit 2] and enabled in bit 0 of MSR
IA32_L2_QOS_CFG at address 0xc82.
As with L3 CDP, when L2 CDP is enabled, each CLOS is mapped 1:2 with mask
MSRs, with one mask enabling programmatic control over data fill location
and one mask control over data placement.
The feature is enabled in kernel along with other RDT features.
More detailed L2 CDP hardware information can be found in technical
article: https://software.intel.com/en-us/articles/intel-resource-director-technology-extensions-introducing-the-l2-code-and-data
The first patch fixes a documentation issue. The following five patches
do the real work.
The patches are based on x86/cache branch in tip tree. The patch #3 cannot
be applied to upstream now because of reformatting in arch/x86/include/asm
/cpufeatures.h. But it's easy to rebase the patches to upstream.
Fenghua Yu (6):
x86/intel_rdt: Classify /proc/cpuinfo flag bits and add missing bits
in documentation
x86/intel_rdt: Add L2 Code and Data Prioritization (CDP) support in
documentation
x86/intel_rdt: Enumerate L2 Code and Data Prioritization (CDP) feature
x86/intel_rdt: Add two new resources for L2 Code and Data
Prioritization (CDP)
x86/intel_rdt: Enable L2 CDP in MSR IA32_L2_QOS_CFG
x86/intel_rdt: Turn on/off L2 CDP in kernel parameter
Documentation/admin-guide/kernel-parameters.txt | 3 +-
Documentation/x86/intel_rdt_ui.txt | 14 ++-
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/intel_rdt.c | 68 ++++++++++++--
arch/x86/kernel/cpu/intel_rdt.h | 5 +
arch/x86/kernel/cpu/intel_rdt_rdtgroup.c | 117 ++++++++++++++++++------
arch/x86/kernel/cpu/scattered.c | 1 +
7 files changed, 170 insertions(+), 39 deletions(-)
--
1.8.3.1
next reply other threads:[~2017-12-20 22:54 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-20 22:57 Fenghua Yu [this message]
2017-12-20 22:57 ` [PATCH 1/6] x86/intel_rdt: Classify /proc/cpuinfo flag bits and add missing bits in documentation Fenghua Yu
2018-01-18 8:37 ` [tip:x86/cache] x86/intel_rdt: Update documentation tip-bot for Fenghua Yu
2017-12-20 22:57 ` [PATCH 2/6] x86/intel_rdt: Add L2 Code and Data Prioritization (CDP) support in documentation Fenghua Yu
2018-01-18 8:37 ` [tip:x86/cache] x86/intel_rdt: Add L2CDP " tip-bot for Fenghua Yu
2017-12-20 22:57 ` [PATCH 3/6] x86/intel_rdt: Enumerate L2 Code and Data Prioritization (CDP) feature Fenghua Yu
2018-01-18 8:37 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2017-12-20 22:57 ` [PATCH 4/6] x86/intel_rdt: Add two new resources for L2 Code and Data Prioritization (CDP) Fenghua Yu
2017-12-20 23:22 ` Randy Dunlap
2017-12-20 23:26 ` Yu, Fenghua
2018-01-18 8:38 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2017-12-20 22:57 ` [PATCH 5/6] x86/intel_rdt: Enable L2 CDP in MSR IA32_L2_QOS_CFG Fenghua Yu
2018-01-18 8:38 ` [tip:x86/cache] " tip-bot for Fenghua Yu
2017-12-20 22:57 ` [PATCH 6/6] x86/intel_rdt: Turn on/off L2 CDP in kernel parameter Fenghua Yu
2018-01-18 8:39 ` [tip:x86/cache] x86/intel_rdt: Add command line parameter to control L2_CDP tip-bot for Fenghua Yu
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