From: Luwei Kang <luwei.kang@intel.com>
To: kvm@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
x86@kernel.org, pbonzini@redhat.com, rkrcmar@redhat.com,
linux-kernel@vger.kernel.org, joro@8bytes.org,
Chao Peng <chao.p.peng@linux.intel.com>,
Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v5 06/11] KVM: x86: Add Intel processor trace context for each vcpu
Date: Sun, 4 Mar 2018 20:07:16 +0800 [thread overview]
Message-ID: <1520165241-15819-7-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1520165241-15819-1-git-send-email-luwei.kang@intel.com>
From: Chao Peng <chao.p.peng@linux.intel.com>
Add a data structure to save Intel Processor Trace context.
It mainly include the value of Intel PT host/guest MSRs
and guest CPUID information.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
arch/x86/kvm/vmx.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 7a0e48c..3d0de12 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -589,6 +589,23 @@ static inline int pi_test_sn(struct pi_desc *pi_desc)
(unsigned long *)&pi_desc->control);
}
+struct pt_ctx {
+ u64 ctl;
+ u64 status;
+ u64 output_base;
+ u64 output_mask;
+ u64 cr3_match;
+ u64 addrs[MSR_IA32_RTIT_ADDR_COUNT];
+};
+
+struct pt_desc {
+ u64 ctl_bitmask;
+ u32 range_cnt;
+ u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
+ struct pt_ctx host;
+ struct pt_ctx guest;
+};
+
struct vcpu_vmx {
struct kvm_vcpu vcpu;
unsigned long host_rsp;
@@ -685,6 +702,8 @@ struct vcpu_vmx {
*/
u64 msr_ia32_feature_control;
u64 msr_ia32_feature_control_valid_bits;
+
+ struct pt_desc pt_desc;
};
enum segment_cache_field {
--
1.8.3.1
next prev parent reply other threads:[~2018-03-05 1:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-04 12:07 [PATCH v5 00/11] Intel Processor Trace virtulization enabling Luwei Kang
2018-03-04 12:07 ` [PATCH v5 01/11] perf/x86/intel/pt: Move Intel-PT MSR bit definitions to a public header Luwei Kang
2018-03-04 12:07 ` [PATCH v5 02/11] perf/x86/intel/pt: Change pt_cap_get() to a public function Luwei Kang
2018-03-04 12:07 ` [PATCH v5 03/11] perf/x86/intel/pt: Introduce a new function to get the capability of Intel PT Luwei Kang
2018-03-16 17:28 ` Paolo Bonzini
2018-03-19 7:17 ` Kang, Luwei
2018-03-19 9:04 ` Paolo Bonzini
2018-03-04 12:07 ` [PATCH v5 04/11] KVM: x86: Add Intel Processor Trace virtualization mode Luwei Kang
2018-03-04 12:07 ` [PATCH v5 05/11] KVM: x86: Add Intel Processor Trace cpuid emulation Luwei Kang
2018-03-04 12:07 ` Luwei Kang [this message]
2018-03-04 12:07 ` [PATCH v5 07/11] KVM: x86: Implement Intel Processor Trace context switch Luwei Kang
2018-03-04 12:07 ` [PATCH v5 08/11] KVM: x86: Introduce a function to initialize the PT configuration Luwei Kang
2018-03-04 12:07 ` [PATCH v5 09/11] KVM: x86: Implement Intel Processor Trace MSRs read/write Luwei Kang
2018-03-04 12:07 ` [PATCH v5 10/11] KVM: x86: Set intercept for Intel PT MSRs Luwei Kang
2018-03-04 12:07 ` [PATCH v5 11/11] KVM: x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2018-03-16 17:30 ` Paolo Bonzini
2018-03-19 7:31 ` Kang, Luwei
2018-03-19 9:05 ` Paolo Bonzini
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