[PATCH v2] Optimize C3 entry on Centaur CPUs

[PATCH v2] Optimize C3 entry on Centaur CPUs

[David Wang]

For new Centaur CPUs the ucode will take care of the preservation of
cache coherence between CPU cores in C-states and the other CPU cores
regardless of how deep the C-states are, so it is not necessary to
flush the caches in software before entering C3.

Signed-off-by: David Wang <davidwang@zhaoxin.com>

Changes from v1 to v2:
* 1, Add some Family/Model/Stepping contrains to let this patch only apply
* to new centaur CPUs.       
* 2, The arbiter disable/enable operations maybe needed for old VIA/Centaur
* platform. So, delete "flags->bm_control=0" in patch v1.

---
 arch/x86/kernel/acpi/cstate.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index dde437f..d92a7f3 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -51,6 +51,16 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 	if (c->x86_vendor == X86_VENDOR_INTEL &&
 	    (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
 			flags->bm_control = 0;
+
+	/*
+	 * For all recent Centaur CPUs, the ucode will make sure that each core can keep
+	 * cache coherence with each other while entering C3 type state.
+	 * So, set bm_check to 1 to indicate that the kernel need not execute a cache 
+	 * flush operation (WBINVD) when entering C3 type state.
+	 */
+	if (c->x86_vendor == X86_VENDOR_CENTAUR &&
+	    (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f && c->x86_mask>=0x0e)))
+			flags->bm_check = 1;
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
-- 
1.9.1